VCXO Selection · PLL Troubleshooting · Bench Validation
A VCXO can meet its standalone specification while a synchronization loop still fails to lock, rings during acquisition or produces excessive jitter. Effective selection and debugging require you to check the oscillator, its controller, the output interface and the board as a connected system.
Confirm guaranteed APR, usable VCTRL range, tuning gain and polarity, output compatibility and the loop model. On the bench, establish the clock path first, measure tuning independently where the circuit permits, and compare free-running and locked performance.
This guide focuses on practical selection, bring-up and fault isolation. For VCXO operating principles and a worked pull-range budget, read the VCXO fundamentals and absolute pull range guide.
Define the VCXO Selection Requirements
Begin with the clock-controller and receiver specifications. In an integer-divider PLL, the locked relationship is fout/N = fref/R. The selected nominal VCXO frequency must place the required output inside its guaranteed tuning coverage. A family’s catalogue frequency range does not describe the analog tuning span of one device. [3]
- Frequency and APR: define the target frequency, reference excursion, additional correction and margin. Record which oscillator errors and aging interval the guaranteed APR already includes.
- Control interface: match the specified center voltage, usable voltage window, polarity, gain range, input loading and modulation response to the controller.
- Clock output: confirm CMOS voltage levels or the exact differential interface, receiver common-mode range, coupling, termination, load and enable behavior.
- Timing performance: specify phase noise at relevant offsets and RMS jitter over a defined integration band, with frequency, operating mode and test conditions.
- Operating conditions: include temperature, supply variation, aging, startup, acquisition and any reference-loss or holdover requirements.
APR describes guaranteed correction coverage after the supplier’s stated oscillator-error allowances. Do not subtract an error twice when it is already included. If only tuning relative to the actual free-running center is specified, build the separate center-error budget before assigning usable coverage. [1]
The APR budget example explains that calculation. Adequate static coverage still requires acquisition and stability checks in the actual loop.
Match VCTRL and Loop Gain Before Power-Up
Use the overlap of the two guaranteed voltage ranges
The usable control range is the overlap between the VCXO input specification and the driver’s guaranteed output swing. Include DAC or charge-pump compliance, buffer swing, loading and operating-condition changes. Measure voltage at the oscillator pin; do not assume the command value equals the applied voltage.
Use local gain, correct units and the actual polarity
Model minimum and maximum tuning gain rather than only a typical average slope. Confirm whether the design tool uses Hz/V or rad/s/V; the latter is 2π times the former. At 100 MHz, an illustrative 40 ppm/V equals 4,000 Hz/V, so a small 1 mV change produces approximately 4 Hz of frequency shift. This example is not FCom product data or an integrated jitter prediction. [2]
Choose the detector or controller polarity to produce negative feedback with the measured tuning direction. Recheck the model when changing the VCXO, charge-pump current, divider settings or filter components.
Include added filtering and controller delay
An extra VCTRL filter changes the loop response as well as the coupled noise. Include it, the VCXO modulation response and any digital-controller delay in the stability assessment. Select bandwidth from reference and oscillator noise spectra together with tracking and settling requirements. [4] [6]
Compare FCom VCXO Families by Interface
Use these families as starting points, then confirm the complete ordering configuration and its approved specification. Each model link below opens its official FCom PDF.
Scroll horizontally to view the complete table.
| Family | Official model datasheets | Selection and approval checks |
|---|---|---|
| Standard CMOS VCXO | FVC-3X PDF FVC-5X PDF | Receiver thresholds, capacitive load, enable state, pin assignment and guaranteed tuning coverage. |
| Low-jitter CMOS VCXO | FVC-3P-LJ PDF FVC-5P-LJ PDF FVC-7P-LJ PDF | Ordered frequency, operating mode, APR, VCTRL limits, gain and jitter under matching measurement conditions. |
| Differential VCXO | FVC-3L-PG PDF FVC-5L-PG PDF FVC-7L-PG PDF | Exact LVDS or LVPECL option, common-mode and swing, coupling, termination, routing and tuning compatibility. |
A matching package or family name does not establish interchangeability. Record the approved part number and document revision, and resolve any unclear catalogue entry with FCom before design approval.
Measure Tuning Independently Where the Circuit Permits
A controlled open-loop measurement helps separate oscillator tuning from feedback-loop behavior. Use a permitted test configuration to isolate the controller output, retain required bias or protection, and apply a quiet external voltage within the VCXO’s specified limits. Avoid driving against an enabled DAC or charge pump.
Scroll horizontally to view the complete test diagram.
Sweep within the allowed voltage window in both directions, allowing readings to settle. Record VCTRL, frequency, polarity, local slope and available range. Compare results with the agreed device specification, then restore the closed-loop connection and repeat the relevant system checks.
A Six-Step VCXO and PLL Debug Sequence
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Establish the clock path
Check supply, ground, enable state, receiver loading or termination, reference presence and divider programming. Verify output frequency and amplitude at suitable test points before interpreting the controller’s lock flag.
Record: supply, reference frequency, output frequency, interface and enable state.
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Separate oscillator tuning from the controller
Use the permitted independent tuning test above to establish the actual VCTRL-to-frequency response. If the controller cannot be isolated safely within the board’s intended test configuration, follow the controller’s documented test mode instead.
Record: voltage window, tuning endpoints, local gain, polarity and test loading.
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Observe acquisition and control-voltage headroom
Capture VCTRL during startup and a defined reference change. A voltage near a limit is a clue to investigate tuning coverage, divider settings, reference error, polarity, driver compliance or loading. Use a high-impedance, low-capacitance probe and account for its effect on the filter.
Record: control trajectory, frequency error, settling time and remaining voltage margin.
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Investigate ringing or repeated loss of lock
Compare the measured transient with the loop model. Verify gain units and limits, charge-pump settings, filter values, modulation response and controller delay. Select any filter change from the model and repeat the transient measurement. External VCO/VCXO loop filters must match the actual loop parameters. [6]
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Trace jitter, phase noise and spurs
Compare free-running and locked spectra under matching conditions. Correlate discrete spurs with supply switching, digital activity and DAC updates. Inspect control-node and supply coupling. Compare RMS jitter only with the same integration limits, carrier frequency, mode and loading, while separating typical results from guaranteed limits. [4] [5]
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Validate the operating corners and recovery behavior
Repeat the required startup, reference switching, reference-loss and recovery tests over the specified temperature and supply ranges. Evaluate holdover against an explicit duration and allowable error. A stored control voltage does not remove oscillator or control-source drift.
Record: lock behavior, VCTRL margin, frequency error, jitter conditions and recovery time.
Scroll horizontally to view the complete decision diagram.
Symptom-to-Measurement Troubleshooting Table
Scroll horizontally to view all troubleshooting columns.
| Symptom | Measure first | Investigate |
|---|---|---|
| No usable clock output | Supply, enable state, output waveform and receiver connection. | Pin assignment, startup, incorrect termination, excessive load or measurement setup. |
| VCTRL near an endpoint | Actual pin voltage, reference/output frequencies, tuning endpoints and driver swing. | Wrong nominal frequency or divider ratio, insufficient coverage, reference error, polarity, compliance or loading. |
| Ringing or unstable acquisition | VCTRL and frequency transient compared with the predicted loop response. | Kv units and range, filter values, charge-pump current, added poles and controller delay. |
| Lock flag asserted, jitter too high | Free-running and locked phase noise or jitter under matching conditions. | Reference-noise transfer, supply/control coupling, loop peaking, integration band and instrument limits. |
| Discrete spectral spurs | Spur offsets and their correlation with switching, data activity or DAC updates. | Periodic coupling, reference-related effects, control updates and measurement artifacts. |
| Loss of lock at temperature or supply corners | VCTRL headroom, frequency error, supply at the part and corner-condition tuning range. | Incomplete frequency budget, gain variation, reduced driver swing and interface margins. |
Frequently Asked Questions
Does VCTRL at a rail prove the VCXO is faulty?
It identifies a condition to investigate. Check the expected lock frequency, tuning coverage, reference, dividers, polarity and driver behavior. An independent permitted tuning measurement can help separate device behavior from controller or loop problems.
Does lock detection prove that jitter meets the requirement?
A lock flag reports the controller’s lock criterion. It does not measure phase noise, integrated jitter or spurs. Verify timing performance at the relevant output under the specified conditions.
Can I add an RC filter to VCTRL to reduce noise?
Assess the filter within the complete loop model. Its pole and loading may change bandwidth, settling and stability margin. Verify the revised transient and noise performance before accepting the change.
Can a TCXO replace a VCXO?
A fixed-output TCXO cannot provide a required voltage-control function. A VCTCXO may be a candidate if its tuning coverage, gain, voltage range, output and dynamic response match the controller and system requirements.
Does freezing VCTRL guarantee holdover accuracy?
Holding the last control value does not remove temperature drift, aging or control-source drift. Specify the allowable error and duration, then validate the oscillator and controller strategy over the required conditions.
Request a VCXO and PLL Configuration Review
Send the target frequency, clock-controller part number, supply, output interface and load, required APR, VCTRL window, temperature range and package constraints. Include the jitter integration band, phase-noise limits and acquisition or holdover targets.
For a debugging request, add the schematic around the VCXO and loop filter, divider and controller settings, measured VCTRL, fault conditions, and relevant waveforms or spectra.
Technical Documentation and Review Contact
Article responsibility: FCom Fuji Crystal. Technical references are listed below; model-specific documents are linked in the family table.
Engineering review contact: Contact FCom for configuration-specific limits and supporting data. Learn more about our team and expertise.
Examples describe general engineering methods. Use the agreed part-specific specification and validated system requirements for final approval. A VCXO alone does not establish SyncE or packet-timing compliance.
Technical References
- SiTime AN10020: Definitions of VCXO Specifications .
- SiTime AN10021: VCXO Parameter Trade-offs for PLL Design .
- Analog Devices: Phase-Locked Loop Fundamentals .
- Analog Devices: How the AD951x Clock Clean-Up Function Works .
- Analog Devices MT-008: Converting Oscillator Phase Noise to Time Jitter .
- Analog Devices: AD9525 Evaluation Board User Guide .
