Which differential output can I choose: LVDS or LVPECL?

FCO-5L-PG is offered with LVDS or LVPECL. Choose the option that matches your receiver input standard and termination. LVDS is typically terminated with 100Ω across OUT/OUTN, while LVPECL is commonly terminated with 50Ω to (VDD−2V).

Can I request custom frequencies, screening or test reports?

Yes. Custom frequencies within 10–1500MHz, screening options and test reports can be provided depending on project needs. Share your jitter mask, integration bandwidth and platform interface details to confirm feasibility.

FCom Fuji Crystal

FCO-5L-PG Differential FASTXO (LVDS / LVPECL)

Q: What is the frequency range of FCO-5L-PG?

FCO-5L-PG supports 10MHz to 1500MHz in a 5.0×3.2×1.25mm SMD package. Standard frequencies are available and other frequencies can be provided on request.

Q: Do you provide samples, MOQ and lead time information?

Yes. We support samples and volume supply. MOQ and lead time depend on frequency, output logic, stability/temperature option and test requirements. Contact us with your target frequency, output, VDD and temperature range for a fast quote.

Industry-standard 5.0×3.2×1.25mm SMD differential output FASTXO supporting LVDS or LVPECL. Wide frequency coverage 10–1500MHz with very low RMS phase jitter (0.6ps typ, 12kHz–20MHz) for optical modules, SONET, Fibre Channel, enterprise servers, storage networking and high-speed clock trees.

10–1500MHz LVDS / LVPECL RMS jitter 0.6ps typ 1.2ps max (12kHz–20MHz) Tri-state enable/disable 5.0×3.2×1.25mm

Request RFQ View Datasheet Detailed Specifications

Application Fit

Optical ModulesReference clocks for optics, SERDES clock trees

Storage NetworkingStorage Area Network (SAN), SAS/SATA clocking

Telecom / SONETSONET timing, broadband access infrastructure

Ethernet / Fibre ChannelHigh-speed networking clock distribution

ComputeEnterprise servers, clock distribution for SoCs

PlatformsMicroprocessors, DSP, FPGA reference clocks

Key Features

Frequency range: 10–1500MHz (LVDS or LVPECL configuration)
Standard frequencies: 106.25 / 125 / 133.33 / 150 / 155.52 / 156.25 / 187.5 / 212.5 / 312.5 / 622.08MHz
RMS phase jitter (12kHz–20MHz): 0.6ps typ, 1.2ps max
Tri-state enable/disable input supported
Supply decoupling: place a 0.1µF capacitor as close as possible between VDD and GND pads

Practical note: If your platform uses a specific jitter integration bandwidth or jitter mask, share it when requesting a recommendation to avoid over- or under-spec selection.

Key Specs

Typical lab reference: VDD per table, ambient 25 ± 5°C; RMS phase jitter integrated 12kHz–20MHz (see tables for limits).

Item	Specification
Series	FCO-5L-PG
Type	Differential Output FASTXO
Package	SMD, 5.0×3.2×1.25mm
Output Logic	LVDS or LVPECL (tri-state enable/disable)
Frequency Range	10–1500MHz
Supply Voltage	3.3V / 2.5V
RMS Phase Jitter	0.6ps typ, 1.2ps max (12kHz–20MHz)
Supply Current	50mA max
Start-up Time	10ms max
Aging	±3ppm/yr (1st year @ 25°C)

Detailed Specifications

Unless otherwise specified: VDD per table, ambient 25 ± 5°C, RH 40%–70%. The tables list common specifications; contact FCom Fuji Crystal for special requirements.

Parameters	Symbol	LVPECL				Unit	Notes
		VDD = 3.3V		VDD = 2.5V
		Min	Max	Min	Max
Frequency Range	F	10–1500				MHz	Common spec
Standard Frequency	F(ST)	106.25, 125, 133.33, 150, 155.52, 156.25, 187.5, 212.5, 312.5, 622.08				MHz	Others on request
Supply Current	Icc	—	50	—	50	mA	Max
Rise Time	Tr	—	1.0	—	1.0	ns	Max, 20%–80%
Fall Time	Tf	—	1.0	—	1.0	ns	Max, 20%–80%
Output Level (High)	VoH	2.275	—	1.475	—	V	Output high
Output Level (Low)	VoL	—	1.68	—	0.88	V	Output low
Tri-state Mode (Enable)	VIH	70% VDD	—	70% VDD	—	V	Enable
Tri-state Mode (Disable)	VIL	—	30% VDD	—	30% VDD	V	Disable
RMS Phase Jitter (12kHz–20MHz)	PJ	—	1.2	—	1.2	ps	Max (typ 0.6ps)
Duty Cycle	TH/T	45–55				%	—
Output Load	RL	50Ω, (VDD − 2V)				—	Termination reference
Start-up Time	Tosc	10				ms	Max
Aging	—	±3				ppm/yr	1st year @ 25°C

LVPECL is commonly terminated with 50Ω to (VDD − 2V). For best phase noise and jitter, place a 0.1µF bypass capacitor as close as possible between VDD and GND pads, and keep the return path short.

Parameters	Symbol	LVDS				Unit	Notes
		VDD = 3.3V		VDD = 2.5V
		Min	Max	Min	Max
Frequency Range	F	10–1500				MHz	Common spec
Standard Frequency	F(ST)	106.25, 125, 133.33, 150, 155.52, 156.25, 187.5, 212.5, 312.5, 622.08				MHz	Others on request
Supply Current	Icc	—	50	—	50	mA	Max
Rise Time	Tr	—	1.0	—	1.0	ns	Max, 20%–80%
Fall Time	Tf	—	1.0	—	1.0	ns	Max, 20%–80%
Output Level (High)	VoH	—	1.6	—	1.6	V	Output high
Output Level (Low)	VoL	0.9	—	0.9	—	V	Output low
Tri-state Mode (Enable)	VIH	70% VDD	—	70% VDD	—	V	Enable
Tri-state Mode (Disable)	VIL	—	30% VDD	—	30% VDD	V	Disable
RMS Phase Jitter (12kHz–20MHz)	PJ	—	1.2	—	1.2	ps	Max (typ 0.6ps)
Duty Cycle	TH/T	45–55				%	—
Output Load	RL	100Ω (between OUT and OUTN)				—	Termination reference
Start-up Time	Tosc	10				ms	Max
Aging	—	±3				ppm/yr	1st year @ 25°C

LVDS output is typically terminated with 100Ω across OUT/OUTN at the receiver. Route as a tightly coupled differential pair with controlled impedance and short return loops.

Applications

Differential clocks are selected not only by frequency, but by interface standard, jitter/phase-noise budget, and layout/termination constraints. FCO-5L-PG targets platforms that need low RMS jitter and wide frequency coverage in a compact 5.0×3.2mm footprint.

Optical Modules & High-Speed Links

Optical module reference clocks often sit close to sensitive SERDES blocks. Low RMS jitter helps preserve eye margin and BER when the clock is multiplied or distributed across high-speed domains.

Selection guide: Differential Oscillator Selection Guide for Optical Module Platforms
Platform clocking: Small Data Centers Clocking Guide: Differential Oscillator Matching

Networking, Storage & Data Centers

In servers, switches and storage, differential clocks must match receiver standards (LVDS/LVPECL/HCSL), termination rules and EMI constraints. Use LVDS where 100Ω differential termination is required and LVPECL when the platform expects PECL swings.

Practical overview: Oscillator Electronics for Networking & Storage
Comparison guide: Medium-Sized Data Center Timing Guide: Differential Crystal Oscillator Comparison

PCIe note: Many PCIe platforms specify 100MHz clocks and may require HCSL. If your platform explicitly requires HCSL, share the PCIe generation, jitter mask and SSC needs so we can recommend the correct series (see “Selection Path / Upgrade Options” below).

Phase Noise

Phase noise points below are specified at VDD = 3.3V with fout = 156.25MHz. Use them as practical anchors for noise budgeting and jitter correlation.

Offset Frequency	Phase Noise	Unit	Condition
100Hz	-85	dBc/Hz	VDD = 3.3V, fout = 156.25MHz
1kHz	-105	dBc/Hz	VDD = 3.3V, fout = 156.25MHz
10kHz	-115	dBc/Hz	VDD = 3.3V, fout = 156.25MHz

Jitter is specified as RMS phase jitter integrated from 12kHz to 20MHz. If your system uses a different integration bandwidth or has tight jitter masks, share those limits when requesting a recommendation.

Frequency Stability vs. Temperature Range

Availability is shown for common stability bins. “Δ” indicates conditional support. Stability includes calibration at 25°C, operating temperature range, input voltage variation, load variation, aging (1st year), shock and vibration.

Temperature Range	±25ppm	±50ppm
-10°C to +60°C	○	○
-20°C to +70°C	○	○
-40°C to +85°C	Δ	○

Legend: ○ = available, Δ = conditional, × = not available.

Package Outline & Recommended PCB Land Pattern

FCO-5L-PG differential FASTXO package outline, 5.0×3.2×1.25mm SMD (dimensions in mm) — Industry-standard 5.0×3.2×1.25mm SMD outline. Follow the datasheet land pattern and keep the bypass capacitor (0.1µF) close to VDD/GND pads for best jitter performance.

Pin Function

Pin #	Function
1	NC / Tri-state
2	Tri-state / NC
3	GND
4	Output
5	Comp. Output
6	VDD

Layout guidance: keep the differential pair tightly coupled; avoid routing near switching power nodes (buck inductors, high di/dt loops) and high-edge-rate buses. Add a 0.1µF bypass capacitor next to VDD/GND pads.

Ordering Code / Options

Standard frequencies include 106.25 / 125 / 133.33 / 150 / 155.52 / 156.25 / 187.5 / 212.5 / 312.5 / 622.08MHz. For other frequencies (10–1500MHz), output logic, or stability bins, please contact FCom Fuji Crystal.

Ordering Field	What to Specify
Part Number	FCO-5L-PG
Frequency	Standard list above, or any value within 10–1500MHz (subject to feasibility)
Output Logic	LVDS or LVPECL
Supply Voltage	3.3V or 2.5V
Stability & Temperature Range	±25ppm / ±50ppm and the required operating temperature range
Enable/Disable	Tri-state function (default supported)
Quantity & Lead Time	Sample needs and target volume timeline

Selection Path / Upgrade Options:

Compare footprint family: FCO-5L (Differential Oscillator)
LVDS-focused page: FCO-5L-PG-LVDS
Lower jitter upgrade: FCO-5L-UJ Low Jitter
Other package options: FCO-3L-PG-LVDS · FCO-7L-PG-LVDS

Downloads

Datasheet

Use the datasheet for electrical limits, termination examples, and recommended land pattern.

Download / View PDF

Product Categories

FAQ

What is the frequency range of FCO-5L-PG?

FCO-5L-PG covers 10MHz to 1500MHz depending on configuration. Standard frequencies are available and custom frequencies can be supported on request.

How do I choose between LVDS and LVPECL?

Choose based on your receiver interface and termination rules. LVDS is typically terminated with 100Ω across OUT/OUTN at the receiver. LVPECL is commonly terminated with 50Ω to (VDD − 2V). Always verify the receiving IC reference design before release.

What RMS jitter performance should I expect?

RMS phase jitter is specified over 12kHz–20MHz. Typical jitter is 0.6ps, and the maximum limit is 1.2ps.

What decoupling is recommended for best jitter and phase noise?

Place a 0.1µF bypass capacitor as close as possible between VDD and GND pads, keep the return path short, and route the differential outputs as a tightly coupled pair with controlled impedance.

Do you provide samples, MOQ and lead time?

Yes. Samples and volume supply are supported. MOQ and lead time depend on frequency, output logic, stability/temperature option and test requirements. Share your target frequency, output, VDD and temperature range for a fast RFQ.

Can you support customization (frequency, screening, test reports, packaging)?

Yes. Custom frequencies within 10–1500MHz, screening options and test reports can be provided depending on project needs. Please include your jitter mask, integration bandwidth, and platform interface details.

Need help selecting the right configuration? Send your target frequency, output logic, VDD, temperature range, and jitter mask requirement.

Contact & Quote Request

For pricing, samples, or design-in support for FCO-5L-PG, please send your requirements and we will respond with a recommended configuration.

Email: Fcom@fujicrystal.com
Contact form: https://www.fujicrystal.com/contact.html
Category: Differential Output Oscillators

Application engineering support: include your platform (optics / networking / storage / PCIe), receiver standard (LVDS/LVPECL/HCSL), termination, VDD, temperature range, and jitter integration bandwidth or jitter mask. This reduces bring-up risk and accelerates qualification.

Application Fit

Key Features

Key Specs

Detailed Specifications

Applications

Optical Modules & High-Speed Links

Networking, Storage & Data Centers

Phase Noise

Frequency Stability vs. Temperature Range

Package Outline & Recommended PCB Land Pattern

Pin Function

Ordering Code / Options

Downloads

Datasheet

Product Categories

FAQ

Related Resources

Product

Applications

Knowledge / News

Contact & Quote Request