Is there a minimum order quantity (MOQ) and what is the lead time?

MOQ and lead time depend on frequency, output option, and screening requirements. Share your target frequency and volume to receive a confirmed schedule for samples and mass production.

Do you provide documentation such as test reports or quality certifications?

We can provide supporting documentation based on project needs. Our ISO certifications include ISO9001 and ISO14001; links are provided on this page for reference.

FCO-7L-PG-LVDS Differential Output FASTXO (7.0×5.0mm, 10–1500MHz)

Q: What termination is recommended for LVDS clock outputs?

LVDS is typically terminated with 100Ω across OUT/OUTN at the receiver. Route as a tightly coupled differential pair with controlled impedance.

7.0×5.0mm SMD differential output FASTXO supporting LVDS. Designed for high-speed clocking in enterprise servers, Ethernet, SONET, and FPGA/DSP systems where phase noise and jitter margin are critical.

Frequency up to 1.5GHz 10–1500MHz LVDS RMS jitter: 1.2ps max 0.6ps typ (RMS) Tri-state enable/disable 7.0×5.0mm package

Request RFQ View Datasheet (PDF) View Electrical Specs

Key Features

LVDS differential output for high-speed clock distribution with robust noise immunity
Wide frequency coverage: 10–1500MHz with common data-center and transport frequencies supported
Low RMS phase jitter: 1.2ps max (12kHz–20MHz), 0.6ps typ for jitter-sensitive links
Tri-state enable/disable simplifies clock-tree power management and platform bring-up
7.0×5.0mm SMD package for dense server, switch, router, and optical module designs

Test condition note (quick reference): unless otherwise specified, 25 ± 5°C, RH 40%–70%; phase noise is typical at fout = 156.25MHz per table notes.

Application Fit

Enterprise ServerSAS / SATA clocking, clock distribution

ProcessorsMicroprocessors / DSP / FPGA reference clocks

Access & GridBroadband access, smart grid systems

High-Speed I/OGigabit Ethernet, SAN, SONET

Highlights

Frequency range: 10–1500MHz (LVDS)
Low RMS phase jitter: 1.2ps max (12kHz–20MHz), 0.6ps typ
Tri-state enable/disable for power and clock-tree control
Recommended decoupling: 0.1μF placed close between VDD and GND pads

Key Specs

Item	Specification
Series	FCO-7L-PG-LVDS
Type	Differential Output FASTXO (LVDS)
Package	SMD, 7.0×5.0mm
Output Logic	LVDS (Tri-state enable/disable)
Frequency Range	10–1500MHz
RMS Phase Jitter	1.2ps max (12kHz–20MHz), 0.6ps typ
Stability Options	±25ppm / ±50ppm (see stability table)
Start-up Time	10ms max
Aging	±3ppm/yr (1st year @ 25°C)
Test Condition	25 ± 5°C, RH 40%–70%

Applications

Differential clocks are selected when platforms need tight jitter margin, strong common-mode noise rejection, and predictable signaling across longer routes or higher data rates. FCO-7L-PG-LVDS targets server and networking clock trees where the receiver interface is LVDS and the system budget is defined by PCIe, Ethernet/SerDes, or optical module timing requirements.

Data Centers & Storage

Clock distribution for NICs, switches, and storage controllers where lower integrated jitter reduces link margin pressure
Platform bring-up: tri-state simplifies isolation testing and incremental clock-tree enable
Reference guidance: Small Data Centers Clocking Guide, Medium-Sized Data Center Timing Guide, Large-Scale Data Center Applications

Optical Modules & High-Speed Networking

LVDS clocking for SerDes and PHY reference paths where differential routing and termination discipline matters
Impedance-controlled routing and 100Ω termination across OUT/OUTN at the receiver minimize reflections
Selection guidance: Differential Oscillator Selection Guide for Optical Module Platforms

If your platform requires HCSL (e.g., PCIe reference clocks) rather than LVDS, use the guides below to match output format and jitter masks: PCIe Gen6 Platform Guide and HCSL Crystal Oscillators – Practical Design Guide.

Electrical Specifications

Unless otherwise specified: ambient 25 ± 5°C, RH 40%–70%. Phase noise values are typical and referenced at fout = 156.25MHz (per table notes). For special specifications, please contact our sales team.

Parameters	Symbol	LVPECL				Unit	Condition / Note
		VDD = 3.3V		VDD = 2.5V
		Min	Max	Min	Max
Frequency Range	F	10–1500				MHz	—
Standard Frequency	F(ST)	106.25, 125, 133.33, 150, 155.52, 156.25, 187.5, 212.5, 312.5, 622.08				MHz	Common list; others on request
Supply Current	Icc	—	50	—	50	mA	Max
Transition Time	Tr	—	1.0	—	1.0	ns	Measured from 20%–80%
Transition Time	Tf	—	1.0	—	1.0	ns	Measured from 20%–80%
Output Level	VoH	2.275	—	1.475	—	V	Output High
Output Level	VoL	—	1.68	—	0.88	V	Output Low
Tri-State Mode	VIH	70% Vdd	—	70% Vdd	—	V	Enable
Tri-State Mode	VIL	—	30% Vdd	—	30% Vdd	V	Disable
Phase Noise (Typ.)	PN	100Hz: −94		100Hz: −94		dBc/Hz	At VDD = 3.3V, fout = 156.25MHz
		1kHz: −113		1kHz: −113
		10kHz: −122		10kHz: −122
RMS Phase Jitter (Integrated 12kHz–20MHz)	PJ	—	1.2	—	1.2	ps	Max
Duty Cycle	TH/T	45–55				%	—
Output Load	RL	50Ω, VDD − 2V				—	Termination reference
Start-up Time	Tosc	10				ms	Max
Aging	ppm/yr	±3				ppm/yr	1st year @ 25°C

LVPECL output is commonly terminated with 50Ω to (VDD − 2V). For best phase noise and jitter, place a 0.1μF bypass capacitor as close as possible between VDD and GND pads, keep the return path short, and route the differential pair tightly coupled.

Parameters	Symbol	LVDS				Unit	Condition / Note
		VDD = 3.3V		VDD = 2.5V
		Min	Max	Min	Max
Frequency Range	F	10–1500				MHz	—
Standard Frequency	F(ST)	106.25, 125, 133.33, 150, 155.52, 156.25, 187.5, 212.5, 312.5, 622.08				MHz	Common list; others on request
Supply Current	Icc	—	50	—	50	mA	Max
Transition Time	Tr	—	1.0	—	1.0	ns	Measured from 20%–80%
Transition Time	Tf	—	1.0	—	1.0	ns	Measured from 20%–80%
Output Level	VoH	—	1.6	—	1.6	V	Output High
Output Level	VoL	0.9	—	0.9	—	V	Output Low
Tri-State Mode	VIH	70% Vdd	—	70% Vdd	—	V	Enable
Tri-State Mode	VIL	—	30% Vdd	—	30% Vdd	V	Disable
Phase Noise (Typ.)	PN	100Hz: −94		100Hz: −94		dBc/Hz	At VDD = 3.3V, fout = 156.25MHz
		1kHz: −113		1kHz: −112
		10kHz: −122		10kHz: −122
RMS Phase Jitter (Integrated 12kHz–20MHz)	PJ	—	1.2	—	1.2	ps	Max
Duty Cycle	TH/T	45–55				%	—
Output Load	RL	100Ω (across OUT/OUTN)				—	Typical termination at receiver
Start-up Time	Tosc	10				ms	Max
Aging	ppm/yr	±3				ppm/yr	1st year @ 25°C

LVDS output is typically terminated with 100Ω across OUT/OUTN at the receiver. Route as a tightly coupled differential pair with controlled impedance and short return paths.

Frequency Stability vs Temperature Range

Availability is shown for common stability bins. “△” indicates conditional support. Stability is inclusive of calibration at 25°C, operating temperature range, input voltage variation, load variation, aging (1st year), shock, and vibration.

Temperature Range	±25ppm	±50ppm
−10°C to +60°C	○	○
−20°C to +70°C	○	○
−40°C to +85°C	△	○

Legend: ○ = available, △ = conditional, × = not available.

Package Outline & Recommended PCB Land Pattern

FCO-7L-PG-LVDS differential FASTXO package outline and land pattern, 7.0×5.0mm — Package outline and recommended PCB land pattern (dimensions in mm).

Pin Function

Pin #	Function
1	NC / Tri-State
2	Tri-State / NC
3	GND
4	Output
5	Comp. Output
6	VDD

Design tip: keep the differential pair short and tightly coupled, avoid stubs, and isolate from switching regulators and noisy high-current planes.

Ordering Information

Standard frequencies include: 106.25, 125, 133.33, 150, 155.52, 156.25, 187.5, 212.5, 312.5, 622.08MHz. For other frequencies, output logic, or stability bins, please contact FCom Fuji Crystal.

Ordering Field	What to Specify
Part Number	FCO-7L-PG-LVDS
Frequency	e.g., 156.25MHz / 125MHz / 622.08MHz (or custom)
Output Logic	LVDS
Supply Voltage	3.3V or 2.5V
Stability & Temperature	±25ppm or ±50ppm, and temperature range (−10 to +60°C / −20 to +70°C / −40 to +85°C)
Enable/Disable	Tri-state function (default supported)
Quantity & Lead Time	Target annual volume and sample/production timeline

For best system results, align output logic and termination with the receiving IC reference design. Share your receiver interface, target jitter mask, and any phase-noise limits when requesting a recommendation.

Selection Path / Upgrade Options

If you are comparing footprints, jitter grades, or adjacent families, use these reference links: FAST delivery oscillators, Differential output oscillator family, FCO-3L-PG-LVDS, FCO-5L-PG-LVDS, FCO-7L-UJ (low jitter).

Downloads

Datasheet (PDF): FCO-7L-PG series datasheet
Package outline image: 7.0×5.0mm outline & land pattern

Need platform matching tables for LVDS/LVPECL/HCSL? Oscillator Electronics for Networking & Storage provides a practical interface-oriented view.

FAQ

What is the frequency range of FCO-7L-PG-LVDS?

FCO-7L-PG-LVDS supports 10MHz to 1500MHz with LVDS differential output options.

What termination is recommended for LVDS clock outputs?

LVDS output is typically terminated with 100Ω across OUT/OUTN at the receiver. Route as a tightly coupled differential pair with controlled impedance and short return paths.

What RMS phase jitter is specified?

RMS phase jitter is specified as 1.2ps max integrated from 12kHz to 20MHz. Typical performance is 0.6ps RMS (12kHz–20MHz).

How should I decouple the supply for best phase noise and jitter?

Place a 0.1μF bypass capacitor as close as possible between VDD and GND pads, keep the return path short, and keep the differential pair tightly coupled away from noisy switching nets.

Do you provide samples and how do I request an RFQ?

Yes. We support samples, pilot runs, and volume production. Email your frequency, output (LVDS), VDD, temperature range, stability bin, and quantity to Fcom@fujicrystal.com or use Contact.

Is there an MOQ and what is the lead time?

MOQ and lead time depend on frequency, output option, and screening requirements. Share your target configuration and expected volume to receive a confirmed schedule for samples and mass production.

Can you customize frequency, voltage, or stability options?

Yes. Custom frequencies, supply options, stability bins, and screening can be supported depending on your platform requirements and jitter/phase-noise targets.

Do you provide test reports or quality certifications?

Supporting documentation can be provided based on project needs. ISO references: ISO9001 and ISO14001.

Extra reading (LVDS fundamentals): What Is LVDS? Low-Voltage Differential Signaling Explained.

Contact & Quote Request

For pricing, samples, or design-in support for FCO-7L-PG-LVDS, please send your requirements and we will respond with a recommended configuration.

Email: Fcom@fujicrystal.com
Contact page: https://www.fujicrystal.com/contact.html
Product hub: Differential Output Oscillators
Datasheet: FCO-7L-PG series PDF
Related products: FCO-7L series, FCO-7L-PG-LVDS
ISO certifications: ISO9001, ISO14001

Suggested RFQ fields: output (LVDS), frequency, VDD, operating temperature, stability bin, quantity, and target timeline.
Technical support: share receiver interface, termination scheme, routing constraints, and jitter/phase-noise limits for a faster recommendation.