What frequency ranges are supported by FCO-5L-UJ?

LVPECL supports 100–220MHz. LVDS supports 100–175MHz (3.3V/2.5V/1.8V). HCSL supports 100–135MHz (3.3V/2.5V/1.8V). Standard frequencies include 100MHz, 125MHz, and 156.25MHz (depending on output).

How low is the phase jitter of FCO-5L-UJ and what is the integration bandwidth?

Typical RMS phase jitter is 0.05ps with jitter integrated from 12kHz to 20MHz. The common table specification shows 0.1ps max @156.25MHz (noted at 3.3V).

Does FCO-5L-UJ support tri-state enable/disable?

Yes. The device supports tri-state enable/disable. Logic thresholds are typically VIH ≈ 70% VDD (enable) and VIL ≈ 30% VDD (disable).

What termination is recommended for LVDS and HCSL outputs?

LVDS load is specified as 100Ω between OUT and OUTN. HCSL load is specified as 50Ω to GND. LVPECL termination depends on the receiver; the table lists a 50Ω, VDD–2V load condition.

Do you provide samples and customization for frequency, stability, and output format?

Yes. Samples are available for evaluation, and customization is supported for frequency, output logic, supply voltage, and stability/temperature options. Contact FCom Fuji Crystal with your platform requirements for feasibility confirmation.

Is pricing shown on the page and how do I request an RFQ?

Pricing is quote-based for B2B projects. Use the contact form or email Fcom@fujicrystal.com with frequency, output logic, VDD, operating temperature, and quantity to request an RFQ.

What are typical MOQ and lead time expectations?

MOQ and lead time depend on frequency/output and stability options. FCom Fuji Crystal will confirm the MOQ, sample plan, and volume lead time after reviewing your requirements.

Ultra-Low Jitter Differential Output Oscillator

FCO-5L-UJ Ultra-Low Jitter Differential Output Oscillator

A 5.0×3.2mm SMD differential oscillator engineered for clean clock trees in datacenters, optical modules, and high-speed platforms. Supports LVPECL / LVDS / HCSL with frequencies up to 220MHz (LVPECL) and ultra-low integrated RMS phase jitter. Built to help you meet tight Ethernet/transport and PCIe jitter budgets with predictable signal integrity.

Package 5.0×3.2mm

Outputs LVPECL / LVDS / HCSL

Up to 220MHz (LVPECL)

Jitter 0.05ps typ; 0.1ps max

Tri-state Enable/Disable

Datasheet (PDF) Request RFQ / Sample Downloads

Key Features Key Specs Detailed Specifications Applications Ordering Code / Options Downloads FAQ Support

FCO-5L-UJ differential output oscillator, ultra-low jitter (5.0×3.2mm) — FCO-5L-UJ (5.0×3.2mm) ultra-low jitter differential oscillator

Key Features

Performance highlights

Frequency support up to 220MHz (LVPECL). LVDS up to 175MHz; HCSL up to 135MHz.
Very low RMS phase jitter: 0.05ps typ (12kHz–20MHz); common table spec shows 0.1ps max @156.25MHz (12kHz–20MHz, @3.3V).
Tri-state enable/disable for clock-tree control, sequencing, and power states.
Low phase noise reference (typ): -150 dBc/Hz @10k, -155 dBc/Hz @100k, -160 dBc/Hz @1M.

Integration essentials

Recommended decoupling: place a 0.1µF bypass capacitor as close as possible between VDD and GND.
LVDS termination: 100Ω between OUT and OUTN. HCSL termination: 50Ω to GND.
For dense clocking, keep the return path continuous and minimize discontinuities on the differential pair.

Test table conditions: ambient 25 ± 5°C, relative humidity 40%–70%. Where noted, phase-noise and jitter reference is VDD=3.3V, fout=156.25MHz.

Key Specs

Quick summary for platform matching (verify output logic, VDD, and stability/temperature option in the detailed tables below).

Output logic & frequency

LVPECL: 100–220MHz (3.3V / 2.5V)
LVDS: 100–175MHz (3.3V / 2.5V / 1.8V)
HCSL: 100–135MHz (3.3V / 2.5V / 1.8V)
Standard: 100MHz / 125MHz / 156.25MHz (output-dependent)

Jitter & reliability

RMS phase jitter: 0.05ps typ (12kHz–20MHz)
Table spec: 0.1ps max @156.25MHz (12kHz–20MHz @3.3V)
Start-up: 5ms max
Aging: ±3ppm (1st year @ 25°C)

Detailed Specifications

LVPECL Option (3.3V / 2.5V)

Parameters	Symbol	LVPECL				Units	Notes
		3.3V		2.5V
		Min.	Max.	Min.	Max.
Frequency Range	F	100–220				MHz	Common spec range
Standard Frequency	F(ST)	100 / 125 / 156.25				MHz
Supply Current	Icc	—	65	—	65	mA
Rise Time	Tr	—	0.4	—	0.4	ns	Measured 20%–80%
Fall Time	Tf	—	0.4	—	0.4	ns	Measured 20%–80%
Output Voltage High	VoH	2.215	2.42	1.415	1.64	V	Output High
Output Voltage Low	VoL	1.49	1.68	0.69	0.88	V	Output Low
Tri-State Mode (Enable)	VIH	70% Vdd	—	70% Vdd	—	V	Enable
Tri-State Mode (Disable)	VIL	—	30% Vdd	—	30% Vdd	V	Disable
Phase Noise @10kHz	PN	-150 (Typ.)		-150 (Typ.)		dBc/Hz	Ref: VDD=3.3V, fout=156.25MHz
Phase Noise @100kHz		-155 (Typ.)		-155 (Typ.)
Phase Noise @1MHz		-160 (Typ.)		-160 (Typ.)
RMS Phase Jitter @156.25MHz	PJ	—	0.1	—	0.1	ps	Integrated 12kHz–20MHz (@3.3V)
Duty Cycle	TH/T	45–55				%
Standby Current	Icc(ST)	—	30	—	30	µA	Max
Output Load	RL	50Ω, VDD–2V				/
Start-up Time	Tosc	5				ms	Max
Aging	ppm/yr	±3				ppm/yr	1st year @25°C

LVDS Option (3.3V / 2.5V / 1.8V)

Parameters	Symbol	LVDS						Units	Notes
		3.3V		2.5V		1.8V
		Min.	Max.	Min.	Max.	Min.	Max.
Frequency Range	F	100–175						MHz
Standard Frequency	F(ST)	100 / 125 / 156.25						MHz
Supply Current	Icc	—	35	—	35	—	25	mA
Rise Time	Tr	—	0.3	—	0.3	—	0.4	ns	Measured 20%–80%
Fall Time	Tf	—	0.3	—	0.3	—	0.4	ns	Measured 20%–80%
Differential Output Voltage	Vdiff	0.24	0.45	0.24	0.45	0.24	0.45	V	VOD, OUT–OUTN
Output Voltage High	VoH	—	1.6	—	1.6	—	1.6	V
Output Voltage Low	VoL	0.9	—	0.9	—	0.9	—	V
Tri-State Mode (Enable)	VIH	70% Vdd	—	70% Vdd	—	70% Vdd	—	V	Enable
Tri-State Mode (Disable)	VIL	—	30% Vdd	—	30% Vdd	—	30% Vdd	V	Disable
Phase Noise @10kHz	PN	-150 (Typ.)		-150 (Typ.)		-150 (Typ.)		dBc/Hz	Ref: VDD=3.3V, fout=156.25MHz
Phase Noise @100kHz		-155 (Typ.)		-155 (Typ.)		-155 (Typ.)
Phase Noise @1MHz		-160 (Typ.)		-160 (Typ.)		-160 (Typ.)
RMS Phase Jitter @156.25MHz	PJ	—	0.1	—	0.1	—	0.1	ps	Integrated 12kHz–20MHz (@3.3V)
Duty Cycle	TH/T	45–55						%
Standby Current	Icc(ST)	30						µA	Max
Output Load	RL	100Ω (Between OUT & OUTN)						Ω
Start-up Time	Tosc	—	5	—	5	—	5	ms
Aging	ppm/yr	±3						ppm/yr	1st year @25°C

HCSL Option (3.3V / 2.5V / 1.8V)

Parameters	Symbol	HCSL						Units	Notes
		3.3V		2.5V		1.8V
		Min.	Max.	Min.	Max.	Min.	Max.
Frequency Range	F	100–135						MHz
Standard Frequency	F(ST)	100 / 125						MHz
Supply Current	Icc	—	46	—	46	—	46	mA
Rise Time	Tr	—	0.6	—	0.6	—	0.6	ns	Measured 20%–80%
Fall Time	Tf	—	0.6	—	0.6	—	0.6	ns	Measured 20%–80%
Output Voltage High	VoH	0.6	0.9	0.6	0.9	0.5	1.0	V
Output Voltage Low	VoL	-0.15	0.15	-0.15	0.15	-0.15	0.15	V
Tri-State Mode (Enable)	VIH	70% Vdd	—	70% Vdd	—	70% Vdd	—	V	Enable
Tri-State Mode (Disable)	VIL	—	30% Vdd	—	30% Vdd	—	30% Vdd	V	Disable
Phase Noise @10kHz	PN	-150 (Typ.)		-150 (Typ.)		-150 (Typ.)		dBc/Hz	Ref: VDD=3.3V, fout=156.25MHz
Phase Noise @100kHz		-155 (Typ.)		-155 (Typ.)		-155 (Typ.)
Phase Noise @1MHz		-160 (Typ.)		-160 (Typ.)		-160 (Typ.)
RMS Phase Jitter @156.25MHz	PJ	—	0.1	—	0.1	—	0.1	ps	Integrated 12kHz–20MHz (@3.3V)
Duty Cycle	TH/T	45–55						%
Standby Current	Icc(ST)	30						µA	Max
Output Load	RL	50 to GND						Ω
Start-up Time	Tosc	—	5	—	5	—	5	ms
Aging	ppm/yr	±3						ppm/yr	1st year @25°C

Engineering note: Jitter performance in-system depends on termination networks, receiver input sensitivity, and PCB return-path integrity. Use a solid ground reference, control impedance, and place the 0.1µF decoupling capacitor at the oscillator pads.

Package Outline & Frequency Stability

FCO-5L-UJ differential output oscillator package outline (5.0×3.2mm)

Package outline and recommended PCB land pattern

Frequency stability vs. temperature range

Temp. (°C)	±20 ppm	±25 ppm	±50 ppm
@ -20 ~ 70	○	○	○
@ -40 ~ 85	△	○	○
@ -40 ~ 105	×	×	○
@ -40 ~ 125	×	×	△

○: Available △: Conditional ×: Not available

Stability option includes calibration @25°C, operating temperature range, input voltage variation, load variation, aging (1st year), shock, and vibration.

Applications

Why ultra-low jitter matters in platforms

Datacenter switching & optics: Cleaner reference clocks reduce downstream PLL stress and help margin high-speed SERDES links in clock distribution trees.
Ethernet/transport references: 156.25MHz domains are common in 40G/100G timing trees; integrated jitter is a key contributor to end-to-end link performance.
PCIe & compute platforms: Differential clocks (often 100MHz) demand controlled impedance and appropriate logic selection (HCSL/LVDS/LVPECL) with correct termination.

Selection tip: match output logic to the receiver ecosystem first, then verify frequency range, VDD, and stability grade. For PCIe-focused guidance, review the HCSL design guide and platform notes linked below.

Application & knowledge links

News & design guides: What Is LVDS? · HCSL Crystal Oscillators – Practical Design Guide

Ordering Code / Options

What to specify

Part number: FCO-5L-UJ
Frequency: (e.g., 100 / 125 / 156.25 MHz or custom within range)
Output logic: LVPECL / LVDS / HCSL
Supply voltage: LVPECL (3.3V/2.5V), LVDS/HCSL (3.3V/2.5V/1.8V)
Stability & temp range: choose from the matrix (e.g., -40~85°C ±25ppm, etc.)
Enable/disable: tri-state option confirmation

Selection Path / Upgrade Options: If you are balancing footprint, jitter, and platform logic, compare the standard FCO-5L series and adjacent low-jitter SKUs: FCO-5L, FCO-5L-PG-LVDS, FCO-3L-UJ (smaller), FCO-7L-UJ (alternative).

Fast inquiry (RFQ / sample)

Send your target frequency, output type, voltage, and operating temperature range. We will confirm feasibility and provide a formal quote and sample plan.

Email Sales (Fcom@fujicrystal.com) Support

Downloads

Datasheet

FCO-5L-UJ Ultra-Low Jitter Differential Output Oscillator (5.0×3.2mm) — PDF

For platform matching and termination, review: What Is LVDS? · HCSL Design Guide

Browse related categories

FAQ

Frequency, output, and jitter

What is the max frequency? Up to 220MHz for LVPECL; LVDS up to 175MHz; HCSL up to 135MHz.
Which standard frequencies are supported? 100MHz / 125MHz / 156.25MHz (depending on output type).
What jitter metric is used? RMS phase jitter integrated over 12kHz–20MHz (where indicated).
Does it support tri-state? Yes, tri-state enable/disable is supported (VIH ≈ 70% VDD, VIL ≈ 30% VDD).

MOQ, lead time, samples, customization

Is pricing shown? Pricing is quote-based (B2B). Request an RFQ with your configuration and quantity.
Do you provide samples? Yes. Samples are available for evaluation and platform validation.
What is typical MOQ / lead time? MOQ and lead time depend on frequency/output and stability options; we confirm after reviewing requirements.
Can I customize frequency or stability? Yes—frequency, output logic, VDD, and stability/temperature options can be customized within the series capability.
Packaging / reports? Contact us for packing specification and available test documentation for your project flow.

Support

Need help matching LVPECL/LVDS/HCSL to your receiver, selecting termination, or verifying jitter budgets for PCIe/optics/datacenter platforms? Share your requirements and FCom Fuji Crystal application engineering will recommend the best configuration for validation.

Certifications: ISO9001 · ISO14001

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