FCom Fuji Crystal

FCO-5L Differential Output Crystal Oscillator (5.0×3.2mm)

Q: Which output logic should I choose: LVPECL, LVDS, or HCSL?

Choose based on your clock receiver interface and termination. LVDS typically uses 100Ω across OUT/OUTN. LVPECL commonly uses 50Ω to VDD−2V. HCSL commonly uses 50Ω to GND.

Q: Do you provide samples and customization?

Yes. We support samples, volume production, and custom configurations (frequency, output logic, voltage, stability/temperature). Contact us with your platform and jitter targets for an RFQ.

Q: What are typical MOQ and lead time?

MOQ and lead time depend on frequency and configuration. Share your target frequency, output logic, temperature range, and forecast; we will confirm sample and production lead times in the RFQ response.

Q: Can you provide packaging details and test reports?

We can provide packaging information and supporting documentation (as applicable). Request the documents during RFQ and specify any required screening or test report items.

5.0×3.2mm ceramic SMD differential output oscillator supporting LVPECL / LVDS / HCSL. Designed for Ethernet, telecom, enterprise servers, and reference clocks for ADC/DAC where phase noise and jitter margin matter.

Frequency up to 220MHz HCSL: 100–135MHz Very low RMS jitter: 0.15ps typ Tri-state enable/disable 5.0×3.2mm package

Get a Quote View Datasheet View Electrical Specs

Application Fit

Ethernet & Optical10G Ethernet, Fibre Channel, SONET

Compute & StorageEnterprise servers, SAN & switch fabrics

TelecomLine cards, clock trees, timing modules

ConvertersReference clocks for ADC/DAC

Highlights

Frequency range: 13.5–220MHz (LVPECL/LVDS); 100–135MHz (HCSL)
Standard frequencies: 100MHz, 125MHz, 156.25MHz (others on request)
Supply options: 3.3V / 2.5V (LVPECL); 3.3V / 2.5V / 1.8V (LVDS, HCSL)
RMS phase jitter: 0.15ps typ (12kHz–20MHz); specifications shown per output logic
Recommended decoupling: 0.1µF at VDD–GND pads, shortest return path

Practical note: differential clocks are usually selected “from the receiver backward”. Confirm your receiver standard (LVPECL/LVDS/HCSL), target frequency (for example 100MHz PCIe HCSL), and jitter/phase-noise budget first, then match the oscillator output and termination to the platform reference design.

Quick Specs

Test conditions (unless otherwise specified): 25°C ±5°C, RH 40%–70%, VDD per table.

Item	Specification
Series	FCO-5L
Package	Ceramic SMD, 5.0×3.2mm
Output Logic	LVPECL / LVDS / HCSL (Tri-state enable/disable)
Frequency Range	13.5–220MHz (LVPECL/LVDS); 100–135MHz (HCSL)
RMS Phase Jitter	0.15ps typ, integrated 12kHz–20MHz (spec limits vary by output)
Frequency Stability Options	±25ppm / ±50ppm (see temperature table)
Aging	±3ppm (1st year @ 25°C)
Test Condition	25°C ±5°C, RH 40%–70%

Applications

FCO-5L is built for platforms where the clock distribution chain and the receiver’s jitter tolerance are the limiting factors. In Ethernet/optical line cards, servers and storage fabrics, and PCIe clock trees, a low-jitter differential oscillator helps protect margin across retimers, clock buffers, and high-speed SerDes links.

Choose the output logic to match the platform reference (termination and biasing matter as much as the clock itself): LVDS commonly uses 100Ω across OUT/OUTN, LVPECL is often referenced to (VDD−2V), and HCSL is typically terminated to GND. If you are targeting 100MHz PCIe (HCSL) or 156.25MHz networking clocks (LVPECL/LVDS), align output standard, voltage, and routing constraints early to avoid re-spin risk.

Helpful resources (selection & design-in): Differential Output Oscillators · Differential Oscillator Selection Guide for Optical Module Platforms · PCIe Gen6 Platform (100MHz differential clock matching) · What Is LVDS? · HCSL Crystal Oscillators – Practical Design Guide

Electrical Specifications

Unless otherwise specified: VDD per table, ambient 25°C±5°C, RH 40%–70%. Phase noise values are typical. Please contact our sales team for special specifications.

Parameters	Symbol	LVPECL				Unit	Condition / Note
		VDD=3.3V		VDD=2.5V
		Min	Max	Min	Max
Frequency Range	F	13.5∼220				MHz
Standard Frequency		100 / 125 / 156.25				MHz
Supply Current	Icc	55				mA	Max
Transition Time	Tr/Tf	0.6				nSec	Max (20%–80%)
Output Level	VoH	2.215	2.420	1.415	1.640	V
Output Level	VoL	1.490	1.680	0.690	0.880	V
Tri-State Mode	VIH	70% VDD	—	70% VDD	—	V
Tri-State Mode	VIL	—	30% VDD	—	30% VDD	V
Phase Noise (Typ.)	PN	-143	—	-145	—	dBc/Hz	@10kHz offset (fout=156.25MHz)
	PN	-151	—	-154	—	dBc/Hz	@100kHz offset (fout=156.25MHz)
	PN	-155	—	-155	—	dBc/Hz	@1MHz offset (fout=156.25MHz)
RMS Phase Jitter	PJ	—	1	—	1	pSec	13.5MHz∼80MHz, 12kHz–20MHz @3.3V
RMS Phase Jitter	PJ	—	0.3	—	0.3	pSec	80MHz∼220MHz, 12kHz–20MHz @3.3V
Duty Cycle	D	45∼55		45∼55		%
Stand By Current	Icc	10				µA	Max
Output Load	RL	50Ω, VDD−2V					Termination reference
Start Up Time	Tosc	10				mSec	Max
Aging		±3				ppm	1st year @25°C

LVPECL output is typically terminated with 50Ω to (VDD−2V). Keep the differential pair tightly coupled and place a 0.1µF bypass capacitor near VDD/GND pads to preserve phase noise and jitter.

Parameters	Symbol	LVDS						Unit	Condition / Note
		VDD=3.3V		VDD=2.5V		VDD=1.8V
		Min	Max	Min	Max	Min	Max
Frequency Range	F	13.5∼220						MHz
Standard Frequency		100 / 125 / 156.25						MHz
Supply Current	Icc	35		30		20		mA	Max
Transition Time	Tr/Tf	0.3		0.3		0.5		nSec	Max (20%–80%)
Output Level	Vdiff	0.24	0.45	0.24	0.45	0.24	0.45	V
Output Level	VoH	—	1.6	—	1.6	—	1.6	V
Output Level	VoL	0.9	—	0.9	—	0.9	—	V
Tri-State Mode	VIH	70% VDD	—	70% VDD	—	70% VDD	—	V
Tri-State Mode	VIL	—	30% VDD	—	30% VDD	—	30% VDD	V
Phase Noise (Typ.)	PN	-145	—	-145	—	-142	—	dBc/Hz	@10kHz offset (fout=156.25MHz)
	PN	-153	—	-153	—	-150	—	dBc/Hz	@100kHz offset (fout=156.25MHz)
	PN	-155	—	-155	—	-153	—	dBc/Hz	@1MHz offset (fout=156.25MHz)
RMS Phase Jitter	PJ	—	0.3	—	0.3	—	0.3	pSec	Integrated 12kHz–20MHz @3.3V
Duty Cycle	D	45∼55		45∼55		45∼55		%
Stand By Current	Icc	10						µA	Max
Output Load	RL	100Ω (between OUT & OUTN)
Start Up Time	Tosc	5		5		10		mSec	Max
Aging		±3						ppm	1st year @25°C

LVDS output is typically terminated with 100Ω across OUT/OUTN at the receiver. Route as a tightly coupled differential pair with controlled impedance and short return loops.

Parameters	Symbol	HCSL						Unit	Condition / Note
		VDD=3.3V		VDD=2.5V		VDD=1.8V
		Min	Max	Min	Max	Min	Max
Frequency Range	F	100∼135						MHz
Standard Frequency		100 / 125						MHz
Supply Current	Icc	42		42		30		mA	Max
Transition Time	Tr/Tf	0.6		0.6		0.6		nSec	Max (20%–80%)
Output Level	VoH	0.6	0.9	0.6	0.9	0.55	1.0	V
Output Level	VoL	-0.15	0.15	-0.15	0.15	-0.15	0.15	V
Tri-State Mode	VIH	70% VDD	—	70% VDD	—	70% VDD	—	V
Tri-State Mode	VIL	—	30% VDD	—	30% VDD	—	30% VDD	V
Phase Noise (Typ.)	PN	-145	—	-145	—	-142	—	dBc/Hz	@10kHz offset (fout=156.25MHz)
	PN	-153	—	-153	—	-150	—	dBc/Hz	@100kHz offset (fout=156.25MHz)
	PN	-155	—	-155	—	-153	—	dBc/Hz	@1MHz offset (fout=156.25MHz)
RMS Phase Jitter	PJ	—	0.3	—	0.3	—	0.3	pSec	Integrated 12kHz–20MHz @3.3V
Duty Cycle	D	45∼55		45∼55		45∼55		%
Stand By Current	Icc	10						µA	Max
Output Load	RL	50Ω to GND
Start Up Time	Tosc	10						mSec	Max
Aging		±3						ppm	1st year @25°C

HCSL output is typically terminated with 50Ω to GND at the receiver. Verify the receiver bias/termination requirements before finalizing.

Frequency Stability vs. Temperature Range

Availability is shown for common stability bins. “Δ” indicates conditional support.

Temperature Range	±25ppm	±50ppm
-20°C ~ +70°C	○	○
-40°C ~ +85°C	○	○
-40°C ~ +105°C	×	○
-40°C ~ +125°C	×	Δ

Legend: ○ = available, × = not available, Δ = conditional (please consult FCom Fuji Crystal for feasibility).

Package Outline & Recommended PCB Land Pattern

FCO-5L package outline and recommended PCB land pattern (dimensions in mm) — Package outline and recommended PCB land pattern (dimensions in mm).

Pin Function

Pin #	Function
1	NC / Tri-state
2	Tri-state / NC
3	GND
4	Output
5	Comp. Output
6	VDD

Ordering Information

Standard frequencies include 100MHz / 125MHz / 156.25MHz. For other frequencies, output logic, or stability bins, please contact FCom Fuji Crystal.

Ordering Field	What to Specify
Part Number	FCO-5L
Frequency	e.g., 100MHz / 125MHz / 156.25MHz (or custom)
Output Logic	LVPECL / LVDS / HCSL
Supply Voltage	3.3V / 2.5V (LVPECL); 3.3V / 2.5V / 1.8V (LVDS, HCSL)
Stability & Temp Range	±25ppm or ±50ppm, and operating temperature range
Enable/Disable	Tri-state function (default supported)
Quantity & Lead Time	Target annual volume and sample/production timeline

Selection Path / Upgrade Options: If you need a smaller footprint, enhanced jitter, or a platform-tuned output option, consider these related parts and family pages: FCO-2L, FCO-3L (3.2×2.5mm), FCO-5L-PG (LVDS), FCO-5L-UJ (Ultra Low Jitter), FCO-7L. For system-level guidance, see Small Data Centers Clocking Guide and Medium-Sized Data Center Timing Guide.

Documents & Downloads

Document	Link
Datasheet (PDF)	FCO-5L Differential Output Crystal Oscillator (5.0×3.2mm)
ISO Certifications	ISO9001 \| ISO14001

FCO-5L differential output crystal oscillator package outline, 5.0×3.2mm (5032) — FCO-5L package outline and recommended PCB land pattern (preview). For design-in, follow the datasheet and your platform’s impedance/stack-up rules.

Knowledge & Application Links

FAQ

What is the frequency range of FCO-5L?

LVPECL and LVDS options support 13.5MHz to 220MHz. The HCSL option supports 100MHz to 135MHz.

Which output logic should I choose: LVPECL, LVDS, or HCSL?

Choose based on your receiver interface and termination requirements. LVDS typically uses 100Ω across OUT/OUTN. LVPECL commonly uses 50Ω to VDD−2V. HCSL commonly uses 50Ω to GND. Always confirm the receiver input standard (biasing and amplitude) before release to production.

What jitter should I expect across different frequency ranges?

For LVPECL, PJ is specified as 1ps max from 13.5MHz to 80MHz and 0.3ps max from 80MHz to 220MHz (integrated 12kHz–20MHz @3.3V). LVDS and HCSL options specify 0.3ps max (integrated 12kHz–20MHz @3.3V).

How should I decouple the supply for best phase noise and jitter?

Place a 0.1µF bypass capacitor as close as possible between VDD and GND pads and keep the return path short. Keep the differential pair tightly coupled and avoid routing near noisy switching nets (buck regulators, DDR busses, etc.).

Do you provide samples and customization?

Yes. We support samples, volume production, and customization (frequency, output logic, supply voltage, stability and temperature range). Share your platform (PCIe/Ethernet/optical/ADC-DAC) and jitter targets for a recommended configuration.

What are typical MOQ and lead time?

MOQ and lead time depend on the exact configuration (frequency, output logic, voltage, and stability bin). Send your requirements and forecast; we will confirm sample and production lead times in the RFQ response.

Can you provide packaging details and test reports?

We can provide packaging details and supporting documentation (as applicable). If you require specific screening or test report items, include them in your RFQ so our team can align the configuration and documentation set.

Need a recommendation? Share your receiver standard (LVPECL/LVDS/HCSL), target frequency, supply voltage, operating temperature, and jitter/phase-noise limits. If pricing is not listed, please request an RFQ (samples and volume options are available).