FCO-5C 5.0×3.2mm CMOS XO, 13.7k–160M
SMD 5.0×3.2mm, SPXO
FEATURE
Product Description
FCO-5C — 5.0×3.2 mm SMD CMOS Crystal Oscillator
Compact ceramic package with wide frequency range (13.7 kHz to 160 MHz), low jitter, tri-state enable, and multi-voltage operation. Built for GPS, Ethernet, and industrial clock domains where clean edges and predictable timing margins matter. Samples, volume production, and customization are supported via RFQ.
Overview
The FCO-5C is a general-purpose SMD CMOS crystal oscillator in a 5.0×3.2×1.2 mm ceramic package. It supports 13.7 kHz to 160 MHz output frequencies with 1.8 V / 2.5 V / 3.3 V supply options and a standard 15 pF CMOS load. A precise duty cycle (45–55%) and low phase jitter (≤ 1.0 ps, 12 kHz–20 MHz) make it suitable for clocking digital interfaces and timing domains from consumer to industrial systems.
Learn the basics: What is a clock oscillator? · How crystal oscillators work · Quartz oscillator fundamentals
Standard Frequencies
2.048, 25, 26, 27, 50, 66.667, 100, 125 MHz
Typical Use Cases
- GPS and Mobile devices
- WLAN / Wireless modules
- Fiber / 10G Ethernet
- Netbook / PDA / DSC
Key Features
- Wide output frequency coverage: 13.7 kHz to 160 MHz
- 1.8 V / 2.5 V / 3.3 V operation with low standby: ≤ 10 μA
- Low jitter clock source: ≤ 1.0 ps RMS (12 kHz–20 MHz), period jitter (pk) ≤ 40 ps
- Precise duty cycle 45–55%; fast edge rate (as low as 3 ns at high frequencies)
- CMOS output, 15 pF load; tri-state output enable via Pin 1
- Multiple temperature stability options to ±20/±25/±50 ppm across extended ranges
Key Specs
Test conditions (unless otherwise specified): 25 ± 5 °C, nominal Vdd, CL = 15 pF, 40–70% RH.
Frequency
13.7 kHz – 160 MHz
Standard: 2.048 / 25 / 26 / 27 / 50 / 66.667 / 100 / 125 MHz
Jitter & Timing
≤ 1.0 ps RMS (12 kHz–20 MHz)
Duty cycle 45–55% · Start-up ≤ 5 ms
Electrical
1.8 V / 2.5 V / 3.3 V
CMOS output · CL 15 pF · Tri-state enable (Pin 1)
Applications
Communications
- Fiber / 10G Ethernet & networking timing
- WLAN/WiMAX timing (wireless modules)
- 5G telecom clock domains
Consumer & Mobile
- Smartphones, GPS, PDA, DSC
- Netbooks / tablets
- Test & measurement instruments (clock reference)
Detailed Specifications
Test conditions unless otherwise specified: 25 ± 5 °C, 40–70% RH; load 15 pF. Values shown are typical/maximum as indicated.
| Parameter | Symbol | Min | Typ | Max | Units | Notes |
|---|---|---|---|---|---|---|
| Frequency Range | F | 13.7 k | — | 160 M | Hz | — |
| Supply Voltage | Vdd | — | 1.8 / 2.5 / 3.3 | — | V | Order options |
| Output Load | CL | — | 15 | — | pF | CMOS |
| Duty Cycle | TH/T | 45 | — | 55 | % | — |
| Start-up Time | Tosc | — | — | 5 | ms | — |
| Period Jitter (pk) | — | — | — | 40 | ps | — |
| RMS Phase Jitter | PJ | — | — | 1.0 | ps | 12 kHz–20 MHz |
| Aging (1st year @25 °C) | — | — | — | ±3 | ppm/yr | — |
| Output Level High | VoH | 0.9×Vdd | — | — | V | — |
| Output Level Low | VoL | — | — | 0.1×Vdd | V | — |
| Enable VIH | VIH | 0.7×Vdd | — | — | V | Pin 1 |
| Disable VIL | VIL | — | — | 0.3×Vdd | V | Pin 1 |
For start-up considerations, see Start-up time in crystal oscillators. For long-term drift considerations, learn about crystal oscillator aging.
Current Consumption (Max)
| Frequency Range | 1.8 V | 2.5 V | 3.3 V |
|---|---|---|---|
| 13.7 kHz ≤ Fo ≤ 93 kHz | 1 mA | 1 mA | 1 mA |
| 0.3125 MHz ≤ Fo < 40 MHz | 7 mA | 8 mA | 10 mA |
| 40 MHz ≤ Fo < 75 MHz | 15 mA | 18 mA | 20 mA |
| 75 MHz ≤ Fo < 135 MHz | 25 mA | 30 mA | 35 mA |
| 135 MHz ≤ Fo ≤ 160 MHz | — | 40 mA | 45 mA |
Transition Time (Rise / Fall, Max @ 10–90%, 15 pF)
| Frequency Range | Tr | Tf | Units |
|---|---|---|---|
| 13.7 kHz ≤ Fo ≤ 93 kHz | 50 | 50 | ns |
| 0.3125 MHz ≤ Fo < 100 MHz | 5 | 5 | ns |
| 100 MHz ≤ Fo ≤ 160 MHz | 3 | 3 | ns |
Note: Specs inclusive of calibration @25 °C, operating temperature range, input voltage variation, load variation, aging (1st year), shock, and vibration.
Frequency Stability vs. Temperature Range
| Temp. Range | ±20 ppm | ±25 ppm | ±50 ppm |
|---|---|---|---|
| −20 ~ +70 °C | ● Available | ● Available | ● Available |
| −40 ~ +85 °C | △ Conditional | △ Conditional | ● Available |
| −40 ~ +105 °C | × Not available | △ Conditional | ● Available |
| −40 ~ +125 °C | × Not available | × Not available | △ Conditional |
“Conditional” availability depends on specific frequency and supply options. Please contact us for feasibility and lead time.
Ordering Code / Options
Tell us your target frequency and constraints (interface, jitter budget, temperature range). We will confirm feasibility, MOQ, and lead time in the RFQ reply.
Common Options to Specify
- Frequency (Fo): 13.7 kHz–160 MHz (standard or custom)
- Supply (Vdd): 1.8 V / 2.5 V / 3.3 V
- Output: CMOS, CL 15 pF
- Enable: Tri-state (Pin 1)
- Stability: ±20 / ±25 / ±50 ppm (by temperature range)
- Operating Temp: −20~+70 °C, −40~+85 °C, −40~+105 °C, −40~+125 °C (availability varies)
Selection Path / Upgrade Options
If your design needs lower EMI, stronger margin in harsh environments, or a family-level comparison, use these paths:
Design Notes for Engineers
- Bypass capacitor: Place a 0.1 μF ceramic capacitor close to the Vdd and GND pads to ensure stable operation and low jitter.
- Tri-state control (Pin 1): VIH ≥ 70% Vdd to enable; VIL ≤ 30% Vdd to disable (high-Z). Useful for clock multiplexing and power saving.
- Start-up: Oscillator reaches stable output within ≤ 5 ms after Vdd is applied; consider this in reset sequencing.
- Load: Keep total load capacitance near 15 pF at the receiver to meet timing specs and edge rates.
- Topology reference: See the Pierce crystal oscillator guide for layout and tuning tips.
Practical design reading: Load capacitance & drive level · Barkhausen criterion tips · Key oscillator parameters
Pinout (Top View)
| Pin | Name | Description |
|---|---|---|
| 1 | ST | Tri-state enable (High = Enable) |
| 2 | GND | Ground |
| 3 | OUT | CMOS clock output |
| 4 | Vdd | Supply voltage (1.8 / 2.5 / 3.3 V) |
Package outline: 5.0×3.2×1.2 mm ceramic SMD.
Compare Other CMOS Oscillators
| Model | Package (mm) | Frequency Range | Supply Options | Link |
|---|---|---|---|---|
| FCO-3C | 3.2 × 2.5 × 0.95 | 13.7 kHz – 160 MHz | 1.8 / 2.5 / 3.3 V | Details |
| FCO-6C | 2.0 × 1.6 × — | 13.7 kHz – 160 MHz | 1.8 / 2.5 / 3.3 V | Details |
| FCO-5C | 5.0 × 3.2 × 1.2 | 13.7 kHz – 160 MHz | 1.8 / 2.5 / 3.3 V | This page |
Frequently Asked Questions
What is the start-up time of a crystal oscillator?
FCO-5C starts within ≤ 5 ms after power is applied. Actual time can vary with load, frequency, and power-up ramp; allocate a margin in your reset/power sequencing.
How do I place the bypass capacitor?
Use a 0.1 μF ceramic capacitor from Vdd to GND as close as possible to the device pads to minimize supply impedance and jitter.
Can I put the output in high-impedance?
Yes. Drive Pin 1 low (≤ 0.3×Vdd) to disable the output (Hi-Z). Drive high (≥ 0.7×Vdd) to enable.
What temperature stability can I select?
Options include ±20/±25/±50 ppm, with availability depending on the operating temperature range (see the matrix above).
What are MOQ, lead time, and sample policy?
We support samples, volume production, and custom options. MOQ and lead time depend on frequency, voltage, and stability grade—please send an RFQ with your target specification and application, and we will confirm quickly.
Can FCO-5C be customized?
Yes. Common customizations include frequency, stability binning, operating temperature range, and output requirements. Share your constraints (interface, jitter budget, environment) for evaluation.
Why is pricing not shown on the page?
This is a B2B component with options that affect price (frequency, stability, voltage, temperature, and qualification). For the most accurate quote, please submit an RFQ and include annual volume and target lead time.
Downloads & Resources
- FCO-5C Datasheet (PDF)
- Timing Devices — Product Family
- Explore Crystal Oscillators
- Technical Support / RFQ
Documents & Downloads
Package outline reference for PCB footprint planning.
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