How do I choose CL and the two capacitors?

Start from the crystal’s specified load capacitance CL. Choose Cin and Cout so that CL ≈ (Cin × Cout)/(Cin + Cout) + Cstray. Account for PCB and pin capacitances (Cstray).

What negative resistance margin do I need?

A common rule is |Rneg| ≥ 5 × ESR for general crystals; for 32.768 kHz watch crystals, aim for ≥ 10 × ESR to ensure cold-start and tolerance to aging.

Why won’t my Pierce oscillator start?

Typical reasons include excessive CL, insufficient negative resistance, too small/large Rf, excessive drive level, poor decoupling/layout, or an out-of-spec crystal ESR.

When should I consider a TCXO instead?

If you need sub-ppm stability over temperature or faster lock in GNSS/5G systems, a TCXO is recommended. See FCom’s TCXO products for suitable models.

How do I estimate stray capacitance (Cstray) on real boards?

Include MCU/ASIC pin capacitance, package, pad, and short trace contributions. A practical range is 1–3 pF for compact loops; measure with an LCR meter or back-calculate from frequency offset to refine Cin/Cout.

What Rf/Rs ranges are typical across frequencies?

Rf 1–10 MΩ to bias the inverter; Rs from a few tens to a few hundred ohms for MHz crystals to limit drive and spurs. 32.768 kHz watch crystals require ultra-low drive—follow the datasheet limit and verify cold start.

Pierce Crystal Oscillator – Design Rules & Pitfalls

Q: What is a Pierce crystal oscillator?

A single-inverter, crystal-controlled oscillator that uses two capacitors to provide the required phase shift. It is simple, low-power, and widely used for XTALs from 32.768 kHz to tens of MHz.

What is a Pierce crystal oscillator?

The Pierce is a single-inverter crystal oscillator widely used from 32.768 kHz to tens of MHz. Two capacitors provide the necessary phase shift and define the effective load capacitance seen by the crystal, while the inverter supplies loop gain. For oscillator fundamentals and frequency calculation methods, see How to Find Frequency of Oscillation and our XTAL Oscillator Guide. For a vendor design guide covering CL calculation, startup margin and stability, refer to ST AN2867 – Oscillator Design Guide.

Barkhausen criterion and Pierce XTAL load capacitance relationship; CL ≈ (Cin×Cout)/(Cin+Cout) + Cstray — Figure 2. Barkhausen conditions: |Aβ| ≥ 1, ∠Aβ = 0°. Load capacitance approximation: *CL ≈ (Cin × Cout)/(Cin + Cout) + C_stray*.

Tip: The crystal is specified at a target CL. If your board parasitics (C_stray) are non-negligible, adjust Cin/Cout down to keep the effective CL on target.

Design rules that actually work

1) Choose Cin/Cout from the crystal’s CL

Use the crystal datasheet load capacitance CL and the approximation CL ≈ (Cin × Cout)/(Cin + Cout) + C_stray. Start with Cin ≈ Cout; trim asymmetrically if the inverter input/output parasitics differ.

2) Secure negative resistance margin

Meet Barkhausen with margin: ensure the inverter presents sufficient negative resistance to overcome crystal ESR. A common rule is |R_neg| ≥ 5×ESR (≥ 10× for 32.768 kHz). Increase inverter bias/gain or reduce CL if margin is thin. For a measurement method and safety factor guidance, see TI’s SLAA322 – MSP430 32-kHz Crystal Oscillators.

3) Feedback resistor Rf

Bias the inverter in its linear region. Typical Rf = 1–10 MΩ. Too small: excess bias/drive & power; too large: slow start or no oscillation at cold.

4) Series resistor Rs (drive control)

Use Rs to limit crystal drive and tame spurs. For MHz-range XTALs, tens to a few hundred ohms are common; for 32 kHz XTALs, keep drive ≤ datasheet spec (often <1 µW). Verify by measuring crystal current/voltage swing.

5) Layout & decoupling

Keep XTAL loop compact; place Cin/Cout next to XTAL pins.
Dedicated quiet ground return; avoid digital ground bounce.
Short traces; minimize stray C and leakage. Guard rings help at 32 kHz.
Decouple Vdd near the inverter with local MLCCs (e.g., 100 nF + 1 µF).

Common pitfalls & quick fixes

Too much CL → slow or no start. Reduce Cin/Cout or account for C_stray. Verify |R_neg| margin.

Over-drive → aging/shock sensitivity. Increase Rs or reduce inverter drive. Keep power within spec.

Rf chosen poorly. If start-up fails at low temp/voltage, try smaller Rf (e.g., 2.2 MΩ → 1 MΩ).

Noisy supply / long loop. Improve decoupling and shrink loop area; route away from clocks/RF.

Wrong crystal ESR. Ensure crystal ESR is within the MCU/ASIC oscillator’s capability.

32.768 kHz specifics (watch crystals)

Target higher margin: |R_neg| ≥ 10×ESR.
Drive power is tiny (often <1 µW). Validate with scope and known load.
Guard the node; humidity/leakage can kill start-up.
Temperature + shock (g-sensitivity) matter—mechanical placement helps.

Recommended models

Measuring negative resistance (bench method)

Insert a known series resistor in place of the crystal, inject a small AC signal, and measure ΔV/ΔI at the oscillator node.
Compute the small-signal input resistance; the real part (negative) is your R_neg.
Tune Cin/Cout and bias to achieve the desired margin versus crystal ESR.

Instrument setup & safety

Use a low-amplitude stimulus near the intended frequency; avoid over-driving the inverter input.
Ensure proper grounding/isolation; minimize probe capacitance to avoid skewing CL.
Cross-check with device vendor app notes and recommended test points.

For watch-crystal specifics and why RTC oscillators often have tighter negative-resistance margins, see Analog Devices’ design note Crystal Considerations with Real-Time Clocks (RTCs).

Pierce vs Colpitts/Clapp (quick compare)

Comparison: Pierce vs Colpitts vs Clapp oscillators—parts count, start-up ease, phase noise, and typical applications — Figure 3. High-level comparison of common crystal oscillator topologies.

Topology	Parts Count	Start-up Ease	Phase Noise	Typical Use
Pierce	Low	Easy (with margin)	Good for XTAL	MCUs, RTC, general clocking
Colpitts	Medium	Moderate	Good	RF oscillators, VCO bases
Clapp	Medium	Moderate	Very good	Stable RF designs

Reference checklist

✔ Crystal datasheet CL, ESR, drive limit checked
✔ Cin/Cout picked with C_stray budgeted; target CL met
✔ |R_neg| margin ≥ 5×ESR (≥ 10× for 32.768 kHz)
✔ Rf biases inverter (1–10 MΩ typical)
✔ Rs limits drive; measured power within spec
✔ Tight layout, clean ground, solid decoupling
✔ Start-up verified across temp/voltage corners

Further vendor guidance: ST AN2867 · TI SLAA322

FAQ

How do I set Cin/Cout for a given CL?: Use CL ≈ (Cin × Cout)/(Cin + Cout) + C_stray. Start symmetric; trim for parasitics.
What symptoms indicate over-drive?: Large crystal current, excessive waveform amplitude, or premature aging/drift. Increase Rs or reduce gain.
How to improve cold start?: Reduce CL, increase bias (tune Rf), verify |R_neg| margin, and improve decoupling/layout.
When is a TCXO better?: When stability over temperature is critical (GNSS, 5G backhaul, test & measurement). See our TCXO portfolio.

Explore Models See TCXO Options Timing Devices Hub

Reviewed by: Senior Application Engineer • Last reviewed on 2025-09-01

Fuji Crystal

Pierce Crystal Oscillator – Design Rules & Common Pitfalls