What is load capacitance (CL) and how do I choose C1/C2?

CL is the capacitance presented to the crystal in the Pierce network. A first-order estimate is CL ≈ (C1×C2)/(C1+C2) + Cstray. Start from the crystal’s specified CL and pick C1≈C2 so (C/2)+Cstray≈CL.

What is drive level (DL) and why does it matter?

Drive level is the power dissipated in the crystal (usually in µW). Excess DL accelerates aging and risks fracture. Keep DL below the data sheet limit (often 100 µW max) and within the recommended operating range (commonly 10–50 µW).

How do I check startup margin?

Ensure the inverter’s negative resistance magnitude |−Rneg| is several times the crystal’s motional resistance Rm (≥5× is a practical rule-of-thumb). Excessively large CL or ESR reduces margin and may prevent start-up.

How do stray capacitances affect frequency?

Package and PCB stray capacitance adds to CL and typically pulls the oscillator lower in frequency. Measuring Cstray (including pad, trace, and pin) or budgeting ~1–3 pF helps you choose C1/C2 correctly.

How can I estimate drive level without a crystal tester?

Estimate DL from the oscillation amplitude and the crystal’s equivalent series resistance (ESR): P≈Vrms²/ESR at series resonance, or P≈Irms²×Rm using motional parameters. A series sense resistor and oscilloscope improve accuracy.

Any PCB layout tips for Pierce?

Keep the loop short, place C1/C2 close to the crystal and inverter pins, use a quiet ground reference, and isolate from fast switching nets. Avoid guard traces that add unintended capacitance unless designed deliberately.

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Q: How to size CL & choose C1/C2 (step-by-step)?

Budget Cstray, then solve (C1×C2)/(C1+C2)=CL_spec−Cstray. Start with C1≈C2 so C/2=CL_spec−Cstray, refine with C2>C1 slightly for loop gain, and re‑check startup margin |−Rneg|≥5×Rm across corners.

Q: How to control drive level (DL) without hurting startup?

Target 10–50 µW and stay below the datasheet max. Estimate P≈Vrms²/ESR or P≈Irms²×Rm. If DL is high, lower inverter bias or add modest series resistance; prefer reducing effective CL and improving layout rather than forcing higher drive.

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Pierce Oscillator: Load Capacitance & Drive Level | FCom

Release time:

2025-09-09 12:05

Load Capacitance & Drive Level – How to Size CL & Control DL

Published: September 9, 2025 · By FCom Fuji Crystal

Pierce oscillator CL sizing Drive level control Startup margin

TL;DR: Pick C1/C2 to meet the crystal’s CL, budget stray capacitance, verify negative resistance for start-up, and keep drive level within limits to avoid aging. See our Crystal Oscillators, Timing Devices, and TCXOs for ready-to-use solutions.

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Cover: Pierce oscillator with capacitors C1/C2 and crystal, highlighting CL and drive level

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Why CL & DL matter

Two parameters quietly decide whether your Pierce oscillator is rock-solid or temperamental: load capacitance (CL) and drive level (DL). CL sets the operating point and frequency pull. DL governs crystal stress, aging, and long-term stability. Get these right and start-up is quick, jitter is low, and accuracy meets spec—especially when graduating from simple XO to temperature-compensated TCXO or selecting among broader timing devices.

Formulas you actually need

For the Pierce network:

Effective CL (first order): CL ≈ (C1 × C2) / (C1 + C2) + Cstray
Frequency pull (qualitative): increasing CL usually lowers oscillation frequency (pulls negative).
Start-up margin: ensure |−Rneg| ≥ 5 × Rm (rule-of-thumb).
Drive level: P ≈ Irms² × Rm (motional model) or P ≈ Vrms² / ESR near series resonance.

Flow: pick CL, budget Cstray, solve for C1/C2, verify start-up, then check drive level — Formula + sizing flow for a Pierce oscillator. (Image: fcom-pierce-formula-flow.png)

How to Size CL & Control DL

Read the crystal datasheet: capture target load capacitance CL_spec (e.g., 8/10/12 pF), maximum drive level (often 100 µW), ESR, and motional parameters.
Budget/measure stray capacitance Cstray: include pads, traces, and IC pins; as a starting point, small MHz footprints are typically ~1.5–3 pF total, but measure on your board when possible.
Compute C1/C2: solve (C1×C2)/(C1+C2) = CL_spec − Cstray. Start with C1 ≈ C2 = C so C/2 = CL_spec − Cstray; optionally choose C2 > C1 slightly to improve loop gain.
Check startup margin: ensure |−Rneg| ≥ 5×Rm. If marginal, reduce effective CL, tweak the C2:C1 ratio, and/or improve layout instead of increasing drive aggressively.
Estimate/control DL: target 10–50 µW and stay below the datasheet max. Estimate with P ≈ Vrms²/ESR (near series resonance) or P ≈ Irms²×Rm. Lower inverter bias or add modest series resistance if DL is high.
Trim frequency (ppm): if frequency is low, actual Cstray may exceed the budget (effective CL too high). Reduce C1/C2 slightly and re‑verify against the crystal’s load sensitivity curve.
Corner validation: re‑test startup time, amplitude, DL, and frequency at min VDD, Tmin, max ESR; keep production margin.
Layout rules: short loop; place C1/C2 close to the crystal and inverter pins; quiet ground; isolate from fast‑switching nets; avoid unintended guard traces.
Module exception: for TCXO/OCXO/integrated XO modules, the network is internal—do not add external C1/C2 unless specified.

Sizing flow for C1/C2 (worked example)

From data sheet: target CL_spec = 12 pF.
Budget stray: pad+trace+pin Cstray ≈ 2 pF.
Solve for the series part: (C1×C2)/(C1+C2) = CL_spec − Cstray = 10 pF.
Pick ratio: start with C1 ≈ C2 = C ⇒ C/2 = 10 pF ⇒ C ≈ 20 pF.
Refine if needed: a slight C2 > C1 (e.g., 22 pF and 18 pF) often improves loop gain on the inverter side.
Re-verify start-up with your MCU/oscillator IC across min VDD, max ESR, cold temp.

Tip: When moving from XO to TCXO, CL is internal to the module—you should not add external C1/C2 unless specified. For discrete XOs, always check the oscillator IC application note for recommended C1/C2 ranges.

Keeping drive level safe

Most small SMD crystals are rated for max DL around 100 µW. Many run best at 10–50 µW. Excess DL increases aging and can crack the resonator. Use one of these checks:

Sense resistor: insert a small series resistor, measure Irms with a scope probe of known loading, estimate P.
Amplitude method: measure Vrms across the crystal, compute P ≈ Vrms²/ESR (watch probe capacitance!).
IC estimator: some MCUs/clock ICs provide DL/negative-resistance estimators—use them to screen boards.

Reducing DL: lower inverter bias current if adjustable, increase series resistance judiciously, or choose a crystal with higher permissible DL. If start-up becomes marginal, revisit C1/C2 and loop gain rather than pushing DL higher.

CL choices vs. behavior

The table shows typical qualitative trends (device- and layout-dependent):

Comparison: low vs. high CL impact on start-up margin, frequency pull, and jitter — Image table for presentations. See accessible HTML table below for the same content.

Parameter	Lower CL (e.g., 8 pF)	Higher CL (e.g., 18 pF)
Start-up margin	Usually higher (easier start)	Usually lower (harder start)
Frequency pull (vs. stray)	Less sensitive	More sensitive
Power/Drive level	Often lower	Often higher
Jitter susceptibility	Good with clean ground	May improve filtering but can stress start-up
EMI interaction	Less capacitive loading	More capacitive loading

Practical checklist

Use data sheet CL and budget 1–3 pF for stray unless measured.
Start with C1≈C2; consider C2 > C1 slightly for gain.
Verify start-up at cold, min VDD, worst-case ESR.
Measure/estimate DL; target 10–50 µW; keep < spec max.
Keep the loop compact; place parts close; use a quiet ground reference.
For modules (TCXO), do not add external C1/C2 unless required.

Frequently Asked Questions

Does the exact C1:C2 ratio matter?

Yes, but there’s tolerance. C1≈C2 simplifies sizing; slightly larger C2 on the inverter side can increase loop gain. Do not overshoot total CL—excess CL reduces start-up margin.

My frequency is low by ~20–40 ppm. What should I check?

First, measure or re-budget Cstray. If actual Cstray is higher than assumed, effective CL is higher and frequency pulls low. Reduce C1/C2 to restore the target CL.

What’s a reasonable ESR for tiny MHz crystals?

Small MHz SMD crystals often have ESR in the tens of ohms. Always use the device’s data sheet values and design start-up margin accordingly.

Can I raise series resistance to limit drive level?

Yes, within reason. It reduces loop gain and DL, but too much can prevent start-up. Adjust together with C1/C2 and verify margin across corners.

Do TCXOs need CL sizing?

No—TCXOs and other modules have internal networks. Treat them as complete clock sources. For selection, see FCom TCXOs.

How to size CL & choose C1/C2 (step-by-step)?

Budget Cstray, solve (C1×C2)/(C1+C2) = CL_spec − Cstray. Start with C1≈C2 so C/2 = CL_spec − Cstray, then optionally set C2 > C1 slightly to improve loop gain. Verify |−Rneg| ≥ 5×Rm over voltage and temperature.

How to control drive level (DL) without hurting startup?

Keep DL in the 10–50 µW range and below the spec max. Estimate with P ≈ Vrms²/ESR or P ≈ Irms²×Rm. If DL is high, reduce inverter bias or add a modest series resistor, and prefer lowering effective CL/optimizing layout rather than pushing drive higher.

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