FCO-3C 3.2×2.5mm CMOS Oscillator 1.25–125MHz
SMD 3.2×2.5mm, SPXO
FEATURE
Product Description
FCO-3C — 3.2×2.5 mm SMD CMOS Crystal Oscillator
A compact CMOS clock oscillator for WLAN/mobile/STB platforms that need clean edges and predictable timing. Multi-rail supply (1.8/2.5/3.3 V) and tri-state OE simplify power management and clock gating. Designed for production programs with sample, volume, and customization support.
Key Specs
Quick summary for selection; detailed limits and test conditions are listed in the specifications tables below.
1.25–125 MHz (common: 24/26/30/40 MHz)
1.8 V / 2.5 V / 3.3 V options
≤1.0 ps RMS (12 kHz–20 MHz)
Tri-state enable/disable (Pin 1)
Overview
FCO-3C is a small-form SMD CMOS crystal oscillator designed for space-constrained systems that still demand clean clock edges and consistent timing. It supports common supply rails (1.8/2.5/3.3 V), maintains tight 45–55% symmetry across a 15 pF CMOS load, and offers tri-state output control for system power savings. For discrete resonators, see our timing crystals and frequency crystals.
- Standard frequencies: 24 / 26 / 30 / 40 MHz
- Tri-state enable/disable via Pin 1
- Application-ready for WLAN/WiMAX, mobile devices, DSC, set-top boxes, and HDTV
- Recommended 0.1 µF decoupling at Vdd–GND for best performance
Key Features
1.25–125 MHz span with popular telecom & consumer frequencies.
Operates at 1.8 V, 2.5 V, or 3.3 V supply rails.
≤1.0 ps RMS (12 kHz–20 MHz) for clean high-speed clocks.
45–55% duty cycle for easier timing closure.
Detailed Specifications
Electrical Specifications
Test conditions unless otherwise stated: Ta = 25 ± 5 °C, RH = 40–70%.
| Parameter | Symbol | Min | Typ | Max | Units | Notes |
|---|---|---|---|---|---|---|
| Frequency Range | F | 1.25 | — | 125 | MHz | — |
| Standard Frequency | F(ST) | 24, 26, 30, 40 | MHz | — | ||
| Supply Voltage | Vdd | 1.8 / 2.5 / 3.3 | V | Typ. | ||
| Output Load | CL | 15 | pF | CMOS | ||
| Output High | VoH | 0.9×Vdd | — | — | V | — |
| Output Low | VoL | — | — | 0.1×Vdd | V | — |
| Tri-State Enable | VIH | 0.7×Vdd | — | — | V | Pin 1 |
| Tri-State Disable | VIL | — | — | 0.3×Vdd | V | Pin 1 |
| Period Jitter (Pk-to-Pk) | — | — | — | 40 | ps | — |
| RMS Phase Jitter | PJ | — | — | 1.0 | ps | 12 kHz–20 MHz |
| Duty Cycle | TH/T | 45–55 | % | — | ||
| Start-up Time | Tosc | — | — | 2 | ms | — |
| Aging (1st year) | — | ±3 | ppm/yr | At 25 °C | ||
Current Consumption & Transition Time
| Frequency Bin (Fo) | Icc @15 pF | Units |
|---|---|---|
| 1.25 ≤ Fo < 10 MHz | 1.2–1.5 | mA |
| 10 ≤ Fo < 20 MHz | 1.5–2.0 | mA |
| 20 ≤ Fo < 80 MHz | 1.5–3.0 | mA |
| 80 ≤ Fo ≤ 125 MHz | 5–8 | mA |
| Standby (−40~+85 °C) | ≤10 | µA |
| Standby (−40~+125 °C) | ≤20 | µA |
| Frequency Bin (Fo) | Tr / Tf (Max) | Units |
|---|---|---|
| 1.25 ≤ Fo < 10 MHz | 5 / 4 / 3 | ns |
| 10 ≤ Fo < 20 MHz | 4 / 3 / 3 | ns |
| 20 ≤ Fo < 80 MHz | 4 / 3 / 3 | ns |
| 80 ≤ Fo ≤ 125 MHz | 4 / 3 / 3 | ns |
Transition times measured 10–90% at CL = 15 pF.
Frequency Stability vs Temperature Range
| Temp Range | ±20 ppm | ±25 ppm | ±50 ppm |
|---|---|---|---|
| −20 ~ +70 °C | Available | Available | Available |
| −40 ~ +85 °C | Conditional | Conditional | Available |
| −40 ~ +105 °C | Not available | Conditional | Available |
| −40 ~ +125 °C | Not available | Not available | Conditional |
Stability includes calibration @25 °C, operating temperature, input voltage and load variation, aging (1st year), shock & vibration.
Applications
FCO-3C targets designs where edge integrity and timing margin matter, but board area is limited. Low integrated jitter helps reduce eye closure and phase noise coupling into RF/IF paths, while tri-state OE supports clock gating for standby power.
- WLAN / WiMAX modules — low jitter clocks to improve RF transceiver timing and baseband integrity.
- Mobile phone connectivity & basebands — compact footprint with multi-voltage supply for PMIC rails.
- Networking & storage endpoints — stable clocks for SERDES/PHY reference domains and timing closure.
- STB / HDTV / 5G CPE timing — clean pixel/audio clocks and predictable duty cycle.
Compare Other Crystal Oscillators
| Model | Package (mm) | Frequency Range | Supply (V) | Output | Highlights | Link |
|---|---|---|---|---|---|---|
| FCO-1C | 1.6×1.2 | 3–60 MHz | 1.8/2.5/3.3 | CMOS | Ultra-compact | View |
| FCO-2C | 2.5×2.0 | 1.25–125 MHz | 1.8/2.5/3.3 | CMOS | Compact, low jitter | View |
| FCO-3C | 3.2×2.5 | 1.25–125 MHz | 1.8/2.5/3.3 | CMOS | Balanced size & performance | — |
| FCO-6C | 2.0×1.6 | 1–54 MHz* | 1.8/2.5/3.3 | CMOS | Small, efficient | View |
*Typical range shown. Refer to each product page for exact options.
Design Notes
- Decouple Vdd to GND with a 0.1 µF MLCC placed close to the device.
- Pin 1 is logic enable (OE/standby). Ensure valid VIH/VIL thresholds vs. supply rail.
- Observe maximum CMOS load of 15 pF or buffer the output to fan-out multiple loads.
Ordering Code / Options
For fast RFQ and correct cross-qualification, specify these parameters. If you are unsure, share your target clock frequency and end application, and our engineers will recommend the best grade.
| Item | Typical Options |
|---|---|
| Frequency | 1.25–125 MHz (common: 24/26/30/40 MHz) |
| Supply Voltage | 1.8 V / 2.5 V / 3.3 V |
| Output / Load | CMOS, CL = 15 pF |
| Stability / Temp | ±20/±25/±50 ppm across multiple temperature grades |
| Control Pin | Tri-state OE / standby (Pin 1) |
If you need tighter stability, wider temperature, or special EMI behavior, consider these variants:
- FCO-3C-HP — higher precision grade
- FCO-3C-UP — upgraded performance option
- FCO-3C-WT — wide-temperature option
- FCO-3C-LE — low-EMI option
Prefer a family view? See XO clock oscillator family.
Documents & Downloads
For project bring-up and selection, these references are commonly used:
- How does a quartz oscillator work?
- Xtal oscillator parameters explained
- Start-up time: what impacts it?
Application examples:
Package drawing (reference). For tape & reel, labeling, and outgoing inspection docs, request via RFQ/Contact.
FAQ
How do I use the tri-state enable on Pin 1?
Drive Pin 1 high (≥70% Vdd) to enable the output; drive low (≤30% Vdd) to disable (high-impedance).
What decoupling is recommended?
Place a 0.1 µF bypass capacitor as close as possible between Vdd and GND pads.
What is the RMS phase jitter?
≤1.0 ps integrated from 12 kHz to 20 MHz with CMOS output at 15 pF load.
Which temperature and stability options are available?
Multiple stability options (±20/±25/±50 ppm) across temperature ranges, including −20~+70 °C, −40~+85 °C, and extended ranges depending on configuration.
Do you publish pricing online?
Pricing is quotation-based (no public online price) because it depends on frequency, stability/temperature grade, screening, and order volume. Use RFQ/Contact for a fast quote.
Can I request samples and what information do you need?
Yes—samples are available. Share target frequency, supply voltage, operating temperature range, stability requirement (ppm), output/load condition, and expected annual volume.
What are MOQ and lead time?
MOQ and lead time vary by frequency/grade and screening. Contact us with your target spec and quantity for the confirmed MOQ and production schedule.
Do you support customization and provide packaging/test documentation?
Yes—custom frequency and grade options are supported. Standard packaging is typically tape & reel for SMT; quality documents and test/reliability reports can be provided upon request.
Related Resources & Application Guides
Quality, Compliance & Engineering Support
- ISO 9001 certification: View certificate
- ISO 14001 certification: View certificate
Need help selecting the best grade? Our applications engineers can review your clock tree, power rails, temperature profile, and jitter budget. Use Contact and include your target frequency, interface, and operating conditions.
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