How do I use tri-state enable?

Drive Pin 1 HIGH (≥0.7×Vdd) to enable the output; drive LOW (≤0.3×Vdd) to disable. In disable mode the output is high-impedance (Hi-Z).

What decoupling is recommended?

Place a 0.1 µF bypass capacitor as close as possible between Vdd and GND.

FCO-6C — 2.0×1.6 mm CMOS Crystal Oscillator

Q: What supply voltages are available?

1.8 V, 2.5 V and 3.3 V options are supported.

Q: What are the standard frequencies?

Common standard frequencies include 24 MHz and 26 MHz. Other frequencies are available on request.

Q: Do you offer samples and customization?

Yes. We support samples for validation and can customize frequency, voltage option, stability and temperature grade for volume programs.

Q: What is the MOQ and lead time?

MOQ and lead time depend on frequency/option and order quantity. Contact us with your target specs for an RFQ and delivery schedule.

Q: Do you provide a price list?

We do not publish a fixed price list. Pricing depends on frequency, voltage, stability, temperature grade and quantity. Please request an RFQ.

Q: Can you provide test reports and quality documents?

Yes. We can provide standard quality documentation and, if required, test reports based on your specification and sampling plan.

Compact SMD XO for space-constrained designs. Ideal for WLAN/WiMax, mobile phones, DSC/HDTV, and set-top boxes. 1.8/2.5/3.3 V options with tri-state enable.

Summary (typical conditions): 25 ± 5 °C, 15 pF load, Vdd nominal. For exact limits, refer to the detailed table and the datasheet.

1.5–50 MHz 45–55% duty ≤2 ms start-up 1.0 ps RMS phase jitter

Request an RFQ Contact Detailed Specs Downloads FAQ

Supply options: samples for validation, volume production, and custom frequency/stability programs.

FCO-6C CMOS crystal oscillator, 2.0×1.6 mm SMD package, low jitter — FCO-6C CMOS crystal oscillator, 2.0×1.6 mm SMD package.

Key Features

Ultra-compact SMD package (typ. 2.05 × 1.65 × 0.75 mm)
CMOS output with tight symmetry (45–55%) — see crystal oscillator parameters
Supply choices: 1.8 V / 2.5 V / 3.3 V
Tri-state enable/disable (Pin 1) — see how crystal oscillators work
RMS phase jitter: 1.0 ps (12 kHz–20 MHz), period jitter pk: 40 ps — for system impact, see oscillator electronics applications
Fast start-up (≤ 2 ms)

Key Specs

At-a-glance summary for quick evaluation (confirm with datasheet for your frequency, voltage and temperature grade).

Frequency Range	1.5–50 MHz (standard: 24 MHz, 26 MHz)
Supply Voltage	1.8 V / 2.5 V / 3.3 V
Output	CMOS, 15 pF load
Enable / Disable	Tri-state (Pin 1), Hi-Z when disabled

Duty Cycle	45–55%
Start-up Time	≤ 2 ms
Phase Jitter	1.0 ps RMS (12 kHz–20 MHz)
Package	2.05 × 1.65 × 0.75 mm (typ.)

Applications

FCO-6C is used where board area is limited but clock quality still matters. Low RMS jitter and clean CMOS edges support reliable digital interfaces and RF baseband clocking.

WLAN / WiMax modules — jitter margin helps maintain BER in high-speed links
Mobile phones and tablets — small footprint enables dense layouts
DSC / HDTV — stable clocking supports audio/video timing
Oscillator clock applications overview

Set-top boxes — tight duty cycle helps downstream logic meet setup/hold
Networking & storage — stable clocks reduce packet/PHY timing stress
5G telecom subsystems — low-jitter clocks are critical for RF/DSP timing budgets
Networking & storage timing

More use cases: Oscillator in 5G telecom, Using a 16 MHz oscillator, Test & measurement timing.

Detailed Specifications

Parameter	Symbol	Min	Typ	Max	Unit	Notes
Frequency Range	F	1.5	—	50	MHz	Standard: 24, 26 MHz available
Supply Voltage	Vdd	—	1.8 / 2.5 / 3.3	—	V	CMOS output
Current (15 pF load)	Icc	—	—	15	mA	Max
Standby Current	Icc(ST)	—	—	10	µA	Disable = tri-state
Output Load	CL	—	15	—	pF	CMOS
Output High	VoH	0.9×Vdd	—	—	V	CMOS
Output Low	VoL	—	—	0.1×Vdd	V	CMOS
Enable (Pin 1)	VIH	0.7×Vdd	—	—	V	Output enabled
Disable (Pin 1)	VIL	—	—	0.3×Vdd	V	Output high-Z
Duty Cycle	TH/T	45	—	55	%	CMOS, 50% ±5%
Rise/Fall Time (1.5 ≤ F < 20 MHz)	Tr/Tf	—	—	5 / 4	ns	@10–90%, 15 pF
Rise/Fall Time (20 ≤ F < 50 MHz)	Tr/Tf	—	—	4 / 3	ns	@10–90%, 15 pF
Period Jitter (pk)	—	—	—	40	ps	Typical
RMS Phase Jitter	PJ	—	—	1.0	ps	12 kHz–20 MHz
Start-up Time	Tosc	—	—	2	ms	Max
Aging (first year @25 °C)	—	—	±3	—	ppm/yr	Typical

Test conditions unless otherwise stated: 25 ± 5 °C, RH 40–70%.

Frequency Stability Options vs. Temperature

Operating Temperature	±20 ppm	±25 ppm	±50 ppm
−20 ~ +70 °C	Available	Available	Available
−40 ~ +85 °C	Conditional	Conditional	Available
−40 ~ +105 °C	Not available	Conditional	Available
−40 ~ +125 °C	Not available	Not available	Conditional

Stability is inclusive of calibration @25 °C, operating temperature range, input voltage/load variation, aging (1st year), shock and vibration.

Design & Layout Guidelines

Place a 0.1 µF bypass capacitor as close as possible between Vdd and GND to ensure optimal oscillator performance — see Pierce crystal oscillator layout tips.
Keep the output trace short and routed over a continuous ground reference to minimize jitter and EMI pickup.
Observe recommended CMOS load (15 pF) for specified timing performance.

Ordering Code / Options

Model: FCO-6C — Frequency: xx.xxxx MHz — Vdd: 1.8 V / 2.5 V / 3.3 V — Symmetry: 45–55%

Selection Path / Upgrade Options

Start with the family overview: XO clock oscillator family (industrial/automotive)
Need general guidance? Crystal-controlled oscillator (XO) overview
For jitter/phase-noise interpretation: What is a clock oscillator? and start-up time considerations

Request an RFQ Datasheet Crystal Oscillators

Note: RFQ-based pricing and lead time depend on frequency, stability, voltage option, temperature grade and quantity.

Documents & Downloads

Datasheet

Download the FCO-6C datasheet for electrical limits, recommended test conditions, and ordering details.

Download Datasheet Request Sample

Package / Outline

Use the outline for footprint and keep-out planning (confirm latest revision in the datasheet).

Related Resources

Knowledge (News)

Applications

Product

Frequently Asked Questions

What supply voltages are available?

1.8 V, 2.5 V and 3.3 V options.

How do I use the tri-state enable?

Drive Pin 1 HIGH (≥ 0.7 × Vdd) to enable the output; LOW (≤ 0.3 × Vdd) to disable. The output becomes high-impedance (Hi-Z) when disabled.

What is the recommended decoupling?

Place a 0.1 µF bypass capacitor close to the device between Vdd and GND.

What are the standard frequencies?

Common standard frequencies include 24 MHz and 26 MHz. Contact us for other frequencies.

Do you offer samples and customization?

Yes. Samples are available for validation, and we support custom frequency/voltage/stability options for volume programs.

What is the MOQ and lead time?

MOQ and lead time depend on frequency/option and quantity. Send your target spec and quantity to receive an RFQ and schedule.

Do you provide a price list?

We do not publish a fixed price list. Pricing is RFQ-based and depends on frequency, stability, temperature grade and quantity.

Can you provide test reports and quality documents?

Yes. We can provide standard quality documentation and, when required, test reports aligned to your specification and sampling plan.

Quality & Compliance

For application engineering support (layout, clock tree, jitter budgeting), contact our technical team via the support form.