FCO-7L Diff Oscillator 220MHz for Telecom
SMD 7.0×5.0mm, Differential Output OSC
FEATURE
Product Description
FCO-7L Differential Output Crystal Oscillator (7.0×5.0 mm)
A compact SMD differential oscillator supporting LVPECL / LVDS / HCSL, built for telecom timing, enterprise servers, and high-speed clock trees. Ultra-low RMS jitter helps protect SerDes and switch/PHY timing budgets when routing clocks across complex boards.
Key Specs (At a Glance)
- Outputs: LVPECL / LVDS / HCSL (tri-state enable/disable)
- Frequency: 13.5–220 MHz (LVPECL/LVDS), 100–135 MHz (HCSL)
- RMS phase jitter: down to 0.3 ps (integrated 12 kHz–20 MHz, per output table)
- Supply: 3.3V / 2.5V (LVPECL), 3.3V / 2.5V / 1.8V (LVDS/HCSL)
- Aging: ±3 ppm/yr (1st year @ 25°C)
Test condition note: Unless otherwise stated, tables reference 25 ± 5°C and 40%–70% RH.
Why FCO-7L
- Designed for controlled-impedance differential routing in dense clock-tree layouts.
- Low-jitter clocking helps protect margin in high-speed links and precision data conversion.
- Tri-state control supports platform power states and clock gating strategies.
Need a platform match (PCIe clocks, optical modules, or data center timing)? See Guides & Links.
Key Features
- Frequency support up to 220 MHz (LVPECL/LVDS).
- Very low RMS phase jitter (integrated 12 kHz–20 MHz) suitable for high-speed timing budgets.
- Tri-state enable/disable for clock gating and system power modes.
- Designed for controlled-impedance differential routing and robust board-level integration.
Electrical limits and test conditions are summarized in the tables below. For special requirements, contact FCom@fujicrystal.com.
Typical Applications
- 10Gbit Ethernet, Fiber Channel
- Storage Area Network (SAN), SONET
- Enterprise Servers, Telecom equipment
- Reference clocks for ADC and DAC
These platforms often require specific differential standards (LVPECL/LVDS/HCSL) and tight jitter budgets to maintain link stability and reduce BER.
Related Products
- FCO-2L (Differential Output OSC)
- FCO-3L (Differential Output OSC)
- FCO-5L (Differential Output OSC)
- FCO-7L-PG-LVDS (LVDS-focused option)
- FCO-7L-UJ (Ultra Low Jitter option)
Applications: Why These Specs Matter
Telecom & Transport (SONET / Sync networks)
- Low jitter reduces timing noise injected into downstream clock recovery and synchronization loops.
- LVPECL/LVDS options help match legacy and modern line-card clocking standards.
Servers & Data Centers (switches, NICs, storage)
- Clock-tree integrity depends on correct output standard and termination across long routes.
- Tri-state supports platform power modes while maintaining deterministic bring-up.
PCIe & High-Speed Digital Clocks
- HCSL is widely used in PCIe ecosystems (typ. 100 MHz) with specific termination practices.
- Phase jitter directly impacts system margin for high-speed serial links.
Data Conversion (ADC/DAC reference)
- Low phase noise/jitter helps preserve SNR and SFDR in clock-limited converter architectures.
- Frequency flexibility supports common sampling clock plans and platform-specific synthesis.
Detailed Specifications
Test condition (common): ambient temperature 25 ± 5°C, relative humidity 40%–70%. Phase noise conditions are referenced at fout = 156.25 MHz where applicable.
| Parameters | Symbol | 3.3V | 2.5V | Units | Notes | ||
|---|---|---|---|---|---|---|---|
| Min. | Max. | Min. | Max. | ||||
| Frequency Range | F | 13.5 ~ 220 | MHz | ||||
| Standard Frequency | F(ST) | 100, 125, 156.25 | MHz | ||||
| Supply Current | Icc | — | 55 | — | 55 | mA | |
| Transition Time (Rise) | Tr | — | 0.6 | — | 0.6 | ns | Measured from 20% ~ 80% |
| Transition Time (Fall) | Tf | — | 0.6 | — | 0.6 | ns | Measured from 20% ~ 80% |
| Output Level (High) | VoH | 2.215 | 2.42 | 1.415 | 1.64 | V | Output High |
| Output Level (Low) | VoL | 1.49 | 1.68 | 0.69 | 0.88 | V | Output Low |
| Tri-State Mode (Enable) | VIH | 70% Vdd | — | 70% Vdd | — | V | Enable |
| Tri-State Mode (Disable) | VIL | — | 30% Vdd | — | 30% Vdd | V | Disable |
| Phase Noise @ 10 kHz (Typ.) | PN | — | -143 | — | -145 | dBc/Hz | At VDD=3.3V, fout=156.25MHz |
| Phase Noise @ 100 kHz (Typ.) | PN | — | -151 | — | -154 | dBc/Hz | At VDD=3.3V, fout=156.25MHz |
| Phase Noise @ 1 MHz (Typ.) | PN | — | -155 | — | -155 | dBc/Hz | At VDD=3.3V, fout=156.25MHz |
| RMS Phase Jitter (13.5–80MHz) | PJ | — | 1 | — | 1 | ps | Integrated 12 kHz ~ 20 MHz |
| RMS Phase Jitter (80–220MHz) | PJ | — | 0.3 | — | 0.3 | ps | Integrated 12 kHz ~ 20 MHz (@3.3V) |
| Duty Cycle | TH/T | 45 ~ 55 | % | ||||
| Stand by Current | Icc(ST) | — | 10 | — | 10 | µA | |
| Output Load | RL | 50Ω, VDD − 2V | — | ||||
| Start-up Time | Tosc | — / 10 | ms | Max | |||
| Aging | ppm/yr | ±3 | ppm/yr | 1st year at 25°C | |||
Note: The table shows common spec. If you have special spec requirements, please contact our salesperson.
| Parameters | Symbol | 3.3V | 2.5V | 1.8V | Units | Notes | |||
|---|---|---|---|---|---|---|---|---|---|
| Min. | Max. | Min. | Max. | Min. | Max. | ||||
| Frequency Range | F | 13.5 ~ 220 | MHz | ||||||
| Standard Frequency | F(ST) | 100, 125, 156.25 | MHz | ||||||
| Supply Current | Icc | — | 35 | — | 30 | — | 20 | mA | |
| Transition Time (Rise) | Tr | — | 0.3 | — | 0.3 | — | 0.5 | ns | Measured from 20% ~ 80% |
| Transition Time (Fall) | Tf | — | 0.3 | — | 0.3 | — | 0.5 | ns | Measured from 20% ~ 80% |
| Output Level (Vdiff) | Vdiff | 0.24 | 0.45 | 0.24 | 0.45 | 0.24 | 0.45 | V | VOD, OUT-OUTN |
| Output Level (VoH) | VoH | — | 1.6 | — | 1.6 | — | 1.6 | V | |
| Output Level (VoL) | VoL | 0.9 | — | 0.9 | — | 0.9 | — | V | |
| Tri-State Mode (Enable) | VIH | 70% Vdd | — | 70% Vdd | — | 70% Vdd | — | V | Enable |
| Tri-State Mode (Disable) | VIL | — | 30% Vdd | — | 30% Vdd | — | 30% Vdd | V | Disable |
| RMS Phase Jitter | PJ | — | 0.3 | — | 0.3 | — | 0.3 | ps | Integrated 12 kHz ~ 20 MHz @ 3.3V |
| Duty Cycle | TH/T | 45 ~ 55 | % | ||||||
| Stand by Current | Icc(ST) | 10 | µA | Max | |||||
| Output Load | RL | 100Ω (Between OUT & OUTN) | Ω | ||||||
| Start-up Time | Tosc | — | 5 | — | 5 | — | 10 | ms | |
| Aging | ppm/yr | ±3 | ppm/yr | 1st year at 25°C | |||||
Note: The table shows common spec. If you have special spec requirements, please contact our salesperson.
| Parameters | Symbol | 3.3V | 2.5V | 1.8V | Units | Notes | |||
|---|---|---|---|---|---|---|---|---|---|
| Min. | Max. | Min. | Max. | Min. | Max. | ||||
| Frequency Range | F | 100 ~ 135 | MHz | ||||||
| Standard Frequency | F(ST) | 100, 125 | MHz | ||||||
| Supply Current | Icc | — | 42 | — | 42 | — | 30 | mA | |
| Transition Time (Rise) | Tr | — | 0.6 | — | 0.6 | — | 0.6 | ns | Measured from 20% ~ 80% |
| Transition Time (Fall) | Tf | — | 0.6 | — | 0.6 | — | 0.6 | ns | Measured from 20% ~ 80% |
| Output Level (VoH) | VoH | 0.6 | 0.9 | 0.6 | 0.9 | 0.55 | 1.0 | V | |
| Output Level (VoL) | VoL | -0.15 | 0.15 | -0.15 | 0.15 | -0.15 | 0.15 | V | |
| Tri-State Mode (Enable) | VIH | 70% Vdd | — | 70% Vdd | — | 70% Vdd | — | V | Enable |
| Tri-State Mode (Disable) | VIL | — | 30% Vdd | — | 30% Vdd | — | 30% Vdd | V | Disable |
| RMS Phase Jitter | PJ | — | 0.3 | — | 0.3 | — | 0.3 | ps | Integrated 12 kHz ~ 20 MHz @ 3.3V |
| Duty Cycle | TH/T | 45 ~ 55 | % | ||||||
| Stand by Current | Icc(ST) | 10 | µA | Max | |||||
| Output Load | RL | 50 to GND | Ω | ||||||
| Start-up Time | Tosc | — | 10 | — | 10 | — | 10 | ms | |
| Aging | ppm/yr | ±3 | ppm/yr | 1st year at 25°C | |||||
Note: The table shows common spec. If you have special spec requirements, please contact our salesperson.
Package Outline & Recommended PCB Land Pattern
Frequency Stability vs. Temperature Range
| Temperature Range | ±25 ppm | ±50 ppm | Notes |
|---|---|---|---|
| @ -20 ~ 70°C | ○ | ○ | |
| @ -40 ~ 85°C | ○ | ○ | |
| @ -40 ~ 105°C | × | ○ | |
| @ -40 ~ 125°C | × | △ |
Stability scope typically includes calibration @25°C, operating temperature range, input voltage variation, load variation, aging (1st year), shock, and vibration.
Ordering Information
What to Provide for a Quote
- Output type: LVPECL / LVDS / HCSL
- Frequency: e.g., 100 / 125 / 156.25 MHz (custom frequencies available within range)
- Supply voltage: 3.3V / 2.5V (LVPECL), 3.3V / 2.5V / 1.8V (LVDS/HCSL)
- Stability & temp range: ±25 ppm or ±50 ppm with target operating range
- Enable/disable requirements: tri-state behavior and logic thresholds (if system-specific)
For special specs (phase noise/jitter, startup, tight stability windows), please include your measurement bandwidth and target application (e.g., SONET/Sync, Ethernet PHY, server clock tree).
Selection Path / Upgrade Options
If your platform calls out a specific interface or tighter jitter, use this quick path:
Example Ordering
Actual ordering codes may vary by your internal rule set. Use the example below to align on configuration, then we confirm the final part number by email.
| Field | Example | Options |
|---|---|---|
| Series | FCO-7L | Differential Output OSC, 7.0×5.0mm |
| Output | LVDS | LVPECL / LVDS / HCSL |
| Frequency | 156.25 MHz | Within supported range (HCSL: 100–135MHz) |
| VDD | 3.3V | Per selected output table |
| Stability | ±50 ppm | ±25 ppm / ±50 ppm |
| Temp Range | -40~85°C | See stability availability table |
Please send your complete requirements to FCom@fujicrystal.com to confirm feasibility and lead time.
Downloads
Datasheet
If you need a specific frequency, output standard, or validation report scope, include it in your RFQ for fastest confirmation.
Quality & Compliance
For documentation requests within applicable scope, contact our team via the support entry below.
Guides & Links (Family / Applications / Knowledge)
Application Guides
- Differential Oscillator Selection Guide for Optical Module Platforms
- PCIe Gen6 Platform: Differential Oscillator Parameter Matching
- Small Data Centers Clocking Guide: Differential Oscillator Matching
- Medium-Sized Data Center Timing Guide: Differential Crystal Oscillator Comparison
- Large-Scale Data Center Applications: Differential Oscillator Use Cases
- Oscillator Electronics for Networking & Storage
Knowledge Articles
- What Is LVDS? Low-Voltage Differential Signaling Explained
- HCSL Crystal Oscillators – Practical Design Guide
- Differential Output Oscillator Product Hub
If your BOM calls out termination or signaling constraints, use the LVDS/HCSL guides above to align interface, routing, and measurement bandwidth.
FAQ
Which output should I choose: LVPECL, LVDS, or HCSL?
Choose the interface that matches your receiver and clock distribution topology. LVPECL is common in telecom timing; LVDS is widely used for low-swing differential distribution; HCSL is frequently used in clock-tree ecosystems but has a narrower frequency range in this series.
What termination is required for each output type?
LVPECL: 50Ω with VDD−2V bias; LVDS: 100Ω between OUT and OUTN; HCSL: 50Ω to GND. Place termination close to the receiver and maintain differential impedance routing.
How do I minimize jitter on my board?
Ensure clean power and grounding (short return path), place a 0.1µF bypass capacitor close between VDD and GND, avoid coupling from noisy switching rails, and keep the differential pair length-matched with controlled impedance.
What does “RMS phase jitter integrated 12 kHz–20 MHz” mean?
It represents integrated timing uncertainty across that offset-band. Use it to budget link/jitter margins, especially for high-speed serial and clock-tree designs. Align measurement bandwidth and filtering to your platform requirements when validating.
Can I request tighter stability or a different temperature range?
Yes. The stability table reflects common offerings. For special stability/temperature windows and system constraints (input voltage variation, shock/vibration), email your requirements for a feasibility check.
Is pricing listed on the website?
To keep quotations accurate to your configuration and volume, pricing is provided by RFQ. Send output type, frequency, VDD, stability, temperature range, and quantity to receive a quote.
What are MOQ and typical lead time? Do you offer samples?
MOQ and lead time depend on configuration and demand. Samples may be available for evaluation, and volume production is supported. Contact us with your requirements and target quantities for confirmation.
Can you customize frequency, output, or provide test reports?
Custom frequencies within the supported range are available, along with output and supply options (LVPECL/LVDS/HCSL). Packaging (tape & reel or tray) and documentation (CoC, test reports per scope) can be discussed during RFQ.
How do I request a quote, sample, or datasheet?
Send output type, frequency, VDD, stability, temperature range, and any phase-noise/jitter targets to FCom@fujicrystal.com, or use the contact page to request RFQ, samples, or the datasheet.
Contact
For datasheet requests, pricing, lead time, custom specifications, or application engineering support:
Note: The tables show common specifications. If you have special requirements (platform compliance, jitter mask targets, measurement bandwidth), please include them in your inquiry.
© FCom Fuji Crystal. All specifications are subject to change without notice. Please confirm final specs for production orders.
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