How do I preserve low jitter on the PCB?

Use the recommended land pattern, place a 0.1µF bypass capacitor as close as possible between VDD and GND pads, route the differential pair with controlled impedance and tight coupling, and keep away from switching noise sources.

Can you provide test reports or compliance documents?

We can provide relevant test information per request (e.g., jitter/phase-noise conditions, inspection details, and quality documents). Tell us your customer compliance checklist when requesting an RFQ.

Ultra-Low Jitter Differential Output Oscillator

FCO-2L-UJ Low-Jitter Diff Osc 2.5×2.0mm

Q: What frequency ranges are supported by FCO-2L-UJ?

LVPECL supports 100–220MHz, LVDS supports 100–175MHz, and HCSL supports 100–135MHz. Standard frequencies include 100MHz, 125MHz, and 156.25MHz depending on output.

Q: How low is the phase jitter of FCO-2L-UJ?

The series highlights very low RMS phase jitter (50fs typ, 12kHz–20MHz). Electrical tables specify RMS phase jitter max 0.1ps at 156.25MHz integrated 12kHz–20MHz @3.3V.

Compact 2.5×2.0mm SMD differential oscillator for high-speed networking, storage and PCIe clocking. Supports LVPECL / LVDS / HCSL, frequency up to 220MHz, with ultra-low RMS phase jitter.

Built for engineers who need clean clocks to protect eye diagrams, margin timing closure, and reduce bit-error risk—without paying the BOM/area penalty of larger packages. Available for samples, volume production, and custom configurations.

Package 2.5×2.0mm

Outputs LVPECL / LVDS / HCSL

Up to 220MHz

Jitter 50fs typ; 0.1ps max

Tri-state Enable/Disable

View Specifications Request RFQ / Sample Download Datasheet

Key Features Key Specs Detailed Specifications Applications Package & Stability Ordering Downloads Internal Links FAQ Contact

FCO-2L-UJ low-jitter differential output oscillator (2.5×2.0mm), LVPECL/LVDS/HCSL — FCO-2L-UJ low-jitter differential output oscillator (2.5×2.0mm)

Key Features

Why FCO-2L-UJ

Frequency support up to 220MHz (LVPECL). LVDS up to 175MHz; HCSL 100–135MHz.
Very low RMS phase jitter: 50fs typ (12kHz–20MHz); table spec shows 0.1ps max @156.25MHz (12kHz–20MHz, @3.3V).
Tri-state enable/disable for clock-tree control and power-state management.
PCB-friendly guidance: place a 0.1µF bypass capacitor close between VDD and GND.

Test conditions referenced in the electrical tables: ambient 25 ± 5°C, relative humidity 40%–70%.

What this enables (practical value)

Networking & optics: lower clock-induced BER and cleaner jitter budgets for SERDES and retimers.
PCIe platforms: match common differential clock interfaces (e.g., 100MHz HCSL) with stable timing.
Instrumentation: reduce phase-noise skirt impact on measurement fidelity and reference clock purity.

Need a specific platform mapping (interface, termination, frequency plan)? Send your target standard and BOM constraints to Fcom@fujicrystal.com.

Key Specs

Electrical Summary

Outputs: LVPECL / LVDS / HCSL
Frequency: 100–220MHz (LVPECL), 100–175MHz (LVDS), 100–135MHz (HCSL)
RMS phase jitter: 50fs typ; 0.1ps max @156.25MHz (12kHz–20MHz, @3.3V)
Start-up: ≤ 5ms (max)
Aging: ±3ppm (1st year @25°C)

Small reminder: the tables below are the source of truth; this summary is for quick screening and RFQ alignment.

Typical Applications

40G/100G Ethernet, MAN: where jitter margin directly affects link robustness and eye opening.
SONET, Fiber Channel: reference clocks that benefit from low integrated jitter and stable switching.
PCIe clock trees: differential clocking (HCSL/LVDS/LVPECL) and routing-friendly small package footprints.
Test instrumentation: clean references for synthesizers, digitizers, and timing modules.

For special specification requirements (frequency / stability / output), please contact FCom Fuji Crystal for configuration support.

Detailed Specifications

Tables below list common specifications. Phase-noise numbers are referenced at VDD=3.3V, fout=156.25MHz where indicated.

LVPECL Option (3.3V / 2.5V)

Parameters	Symbol	LVPECL				Units	Notes
		3.3V		2.5V
		Min.	Max.	Min.	Max.
Frequency Range	F	100–220				MHz	Common spec range
Standard Frequency	F(ST)	100 / 125 / 156.25				MHz
Supply Current	Icc	—	65	—	65	mA
Rise Time	Tr	—	0.4	—	0.4	ns	Measured 20%–80%
Fall Time	Tf	—	0.4	—	0.4	ns	Measured 20%–80%
Output Voltage High	VoH	2.215	2.42	1.415	1.64	V	Output High
Output Voltage Low	VoL	1.49	1.68	0.69	0.88	V	Output Low
Tri-state Enable	VIH	70% VDD		70% VDD		V	Enable
Tri-state Disable	VIL	—	30% VDD	—	30% VDD	V	Disable
Phase Noise (typ/max) @ 10kHz	PN	−150 / −150		−150 / −150		dBc/Hz	At VDD=3.3V, fout=156.25MHz
Phase Noise (typ) @ 100kHz	PN	−155		−155		dBc/Hz	At VDD=3.3V, fout=156.25MHz
Phase Noise (typ) @ 1MHz	PN	−160		−160		dBc/Hz	At VDD=3.3V, fout=156.25MHz
RMS Phase Jitter @156.25MHz	PJ	Max 0.1		Max 0.1		ps	Integrated 12kHz–20MHz @3.3V
Duty Cycle	TH/T	45–55				%
Standby Current	Icc(ST)	—	30	—	30	µA	Max
Output Load	RL	50Ω, VDD − 2V				—	Typical LVPECL termination
Start-up Time	Tosc	Max 5				ms
Aging	ppm/yr	±3				ppm/yr	1st year @25°C

PCB tip: place a 0.1µF bypass capacitor as close as possible between VDD and GND pads. LVPECL typical termination: 50Ω to (VDD − 2V).

LVDS Option (3.3V / 2.5V / 1.8V)

Parameters	Symbol	LVDS						Units	Notes
		3.3V		2.5V		1.8V
		Min.	Max.	Min.	Max.	Min.	Max.
Frequency Range	F	100–175						MHz	Common spec range
Standard Frequency	F(ST)	100 / 125 / 156.25						MHz
Supply Current	Icc	—	35	—	35	—	25	mA
Rise Time	Tr	—	0.3	—	0.3	—	0.4	ns	Measured 20%–80%
Fall Time	Tf	—	0.3	—	0.3	—	0.4	ns	Measured 20%–80%
Differential Output Voltage	Vdiff	0.24	0.45	0.24	0.45	0.24	0.45	V	VOD, OUT–OUTN
Output Voltage High	VoH	—	1.6	—	1.6	—	1.6	V
Output Voltage Low	VoL	0.9	—	0.9	—	0.9	—	V
Tri-state Enable	VIH	70% VDD		70% VDD		70% VDD		V	Enable
Tri-state Disable	VIL	—	30% VDD	—	30% VDD	—	30% VDD	V	Disable
Phase Noise (typ/max) @ 10kHz	PN	−150 / −150		−150 / −150		−150 / −150		dBc/Hz	At VDD=3.3V, fout=156.25MHz
Phase Noise (typ) @ 100kHz	PN	−155		−155		−155		dBc/Hz	At VDD=3.3V, fout=156.25MHz
Phase Noise (typ) @ 1MHz	PN	−160		−160		−160		dBc/Hz	At VDD=3.3V, fout=156.25MHz
RMS Phase Jitter @156.25MHz	PJ	Max 0.1		Max 0.1		Max 0.1		ps	Integrated 12kHz–20MHz @3.3V
Duty Cycle	TH/T	45–55						%
Standby Current	Icc(ST)	Max 30						µA
Output Load	RL	100Ω (between OUT & OUTN)						Ω	Typical LVDS termination
Start-up Time	Tosc	Max 5						ms
Aging	ppm/yr	±3						ppm/yr	1st year @25°C

LVDS typical termination is 100Ω across OUT/OUTN. Place a 0.1µF bypass capacitor close to VDD/GND pads.

HCSL Option (3.3V / 2.5V / 1.8V)

Parameters	Symbol	HCSL						Units	Notes
		3.3V		2.5V		1.8V
		Min.	Max.	Min.	Max.	Min.	Max.
Frequency Range	F	100–135						MHz	Common spec range
Standard Frequency	F(ST)	100 / 125						MHz
Supply Current	Icc	—	46	—	46	—	46	mA
Rise Time	Tr	—	0.6	—	0.6	—	0.6	ns	Measured 20%–80%
Fall Time	Tf	—	0.6	—	0.6	—	0.6	ns	Measured 20%–80%
Output Level (High)	VoH	0.6	0.9	0.6	0.9	0.5	1.0	V
Output Level (Low)	VoL	−0.15	0.15	−0.15	0.15	−0.15	0.15	V
Tri-state Enable	VIH	70% VDD		70% VDD		70% VDD		V	Enable
Tri-state Disable	VIL	—	30% VDD	—	30% VDD	—	30% VDD	V	Disable
Phase Noise (typ/max) @ 10kHz	PN	−150 / −150		−150 / −150		−150 / −150		dBc/Hz	At VDD=3.3V, fout=156.25MHz
Phase Noise (typ) @ 100kHz	PN	−155		−155		−155		dBc/Hz	At VDD=3.3V, fout=156.25MHz
Phase Noise (typ) @ 1MHz	PN	−160		−160		−160		dBc/Hz	At VDD=3.3V, fout=156.25MHz
RMS Phase Jitter @156.25MHz	PJ	Max 0.1		Max 0.1		Max 0.1		ps	Integrated 12kHz–20MHz @3.3V
Duty Cycle	TH/T	45–55						%
Standby Current	Icc(ST)	Max 30						µA
Output Load	RL	50 to GND						Ω	Typical HCSL termination
Start-up Time	Tosc	Max 5						ms
Aging	ppm/yr	±3						ppm/yr	1st year @25°C

HCSL typical termination: 50Ω to GND. Place a 0.1µF bypass capacitor close to VDD/GND pads.

Package Outline & Frequency Stability

FCO-2L-UJ package outline and recommended PCB land pattern (2.5×2.0mm)

Frequency Stability vs. Temperature Range

Temp. Range	±20ppm	±25ppm	±50ppm
−20 to +70°C	○	○	○
−40 to +85°C	△	○	○
−40 to +105°C	×	×	○
−40 to +125°C	×	×	△

Legend: ○ Available, △ Conditional, × Not available. Stability definition is inclusive of calibration @25°C, operating temperature range, input voltage variation, load variation, aging (1st year), shock, and vibration.

Ordering Code / Options

Common Configuration Checklist

Output logic: LVPECL / LVDS / HCSL
Supply: 3.3V / 2.5V / 1.8V (depends on output table)
Frequency: 100 / 125 / 156.25 MHz (standard); other frequencies on request
Stability & temp: ±20/±25/±50ppm with −20~70 / −40~85 / −40~105 / −40~125°C availability
Enable: Tri-state enable/disable supported

For quotation, include: Output, VDD, Frequency, Temp range, Stability, and annual volume.

Selection Path / Upgrade Options: If you need more board margin (larger footprint) or a platform-specific mapping, consider the low-jitter UJ family options: FCO-3C-UJ, FCO-5L-UJ, FCO-7L-UJ.

Example RFQ Line

FCO-2L-UJ / Output: LVDS / VDD: 3.3V / Freq: 156.25MHz / Temp: −40~+85°C / Stability: ±25ppm / Qty: ____ pcs / Application: 100G Ethernet

Contact: Fcom@fujicrystal.com · Contact page

Downloads

Datasheet

FCO-2L-UJ Ultra-Low Jitter Differential Output Oscillator (2.5×2.0mm) — PDF

Need a platform-specific clocking checklist (termination, impedance, routing, jitter budget)? Tell us your standard (PCIe / Ethernet / SONET) and we’ll align a recommendation.

Engineering Support

Sales & RFQ: Fcom@fujicrystal.com
Technical support: share your interface (LVPECL/LVDS/HCSL), frequency plan, and temperature range
Contact page: www.fujicrystal.com/contact.html

Reference note: phase-noise/jitter figures shown are tied to stated conditions in the tables (e.g., VDD and fout). Always validate against your platform’s integration bandwidth and measurement method.

Internal Links (Family / Applications / Knowledge)

Product Family

Applications & Platform Guides

Knowledge (News)

Recommended Low-Jitter UJ Models

Model	Package	Output	Positioning
FCO-3C-UJ	3.2×2.5mm	LVPECL / LVDS / HCSL	More layout margin, broad frequency coverage
FCO-5L-UJ	5.0×3.2mm	LVPECL / LVDS / HCSL	System clocking with more board margin
FCO-7L-UJ	7.0×5.0mm	LVPECL / LVDS / HCSL	Roomier layout for complex clock trees

Quality & compliance: ISO9001, ISO14001.

FAQ

What is the frequency range of FCO-2L-UJ?

LVPECL supports 100–220MHz, LVDS supports 100–175MHz, and HCSL supports 100–135MHz. Standard frequencies include 100MHz, 125MHz, and 156.25MHz (output-dependent).

How low is the phase jitter of FCO-2L-UJ?

The series highlights very low RMS phase jitter (50fs typ, 12kHz–20MHz). The electrical tables specify RMS phase jitter max 0.1ps at 156.25MHz integrated 12kHz–20MHz (@3.3V).

Which output logic should I choose: LVPECL, LVDS, or HCSL?

Choose based on your receiver interface and termination requirements. LVDS typically uses 100Ω across OUT/OUTN. LVPECL commonly uses 50Ω to (VDD−2V). HCSL commonly uses 50Ω to GND. Confirm the target IC input spec before finalizing.

What stability options are available across temperature range?

Common options include ±20/±25/±50ppm, with availability depending on temperature range. The stability matrix on this page shows which combinations are available/conditional/not available. For special requirements, contact FCom Fuji Crystal.

Do you provide samples and customization?

Yes. Samples are available for evaluation, and we support customization on frequency, output logic, stability and temperature range. Share your platform (Ethernet/SONET/PCIe), interface and constraints for fast alignment.

What are MOQ and lead time?

MOQ and lead time depend on configuration (frequency, output, stability, temperature range) and current capacity. Send your requirement and annual volume to receive the most accurate RFQ.

Can you provide packaging information and test reports?

Packaging options and relevant test information can be provided upon request. Include your customer compliance checklist (inspection, test conditions, documentation) when requesting an RFQ.

Contact (RFQ / Sample / Technical Support)

Fast RFQ Checklist

Platform: 40G/100G Ethernet, SONET, PCIe, optical module, instrumentation
Interface: LVPECL / LVDS / HCSL
Frequency: target (e.g., 100MHz / 125MHz / 156.25MHz)
Temp range & stability: −40~+85°C (±25ppm) etc.
Quantity: samples + volume forecast

Email: Fcom@fujicrystal.com · Web: Contact page

Application Engineering Support

Termination guidance (LVDS 100Ω / HCSL 50Ω-to-GND / LVPECL 50Ω-to-(VDD−2V))
Differential routing: impedance control, coupling, aggressor isolation
Jitter budgeting: integration band alignment with platform requirements

Certifications: ISO9001 · ISO14001