Ultra-Low Jitter Differential Output OSC

FCO-3L-UJ (3.2×2.5mm) Ultra-Low Jitter Differential Oscillator

Compact 3.2×2.5mm SMD differential oscillator for high-speed networking and instrumentation. Supports LVPECL / LVDS / HCSL, frequency up to 220MHz, with performance engineered for low phase noise and low integrated jitter. Ideal when platforms demand deterministic clocking margin for SerDes/PLL and clock distribution trees.

Package3.2×2.5mm

OutputsLVPECL/LVDS/HCSL

Max F220MHz

Tri-stateEnable/Disable

View Specifications Request Quote / Sample Package & Stability

Key Features Applications Detailed Specs Package Ordering Downloads Selection Path FAQ Support Contact

FCO-3L-UJ differential oscillator, ultra-low jitter, 3.2×2.5mm SMD (product image) — FCO-3L-UJ ultra-low jitter differential oscillator (3.2×2.5mm)

Key Features

Highlights

Frequency support up to 220MHz (LVPECL). LVDS up to 175MHz; HCSL 100–135MHz.
Designed for low phase noise and low integrated jitter (integration band typically 12kHz–20MHz).
Tri-state enable/disable for clock-tree control and power management.
Layout recommendation: place a 0.1µF bypass capacitor as close as possible between VDD and GND pads.

Engineering notes (termination & routing)

Route differential pairs with controlled impedance and tight coupling; avoid stubs and discontinuities.
Keep clock outputs away from switching regulators, high di/dt nodes, and long parallel runs with aggressors.
Use the output-format-appropriate termination (LVDS 100Ω between OUT/OUTN; LVPECL typical load to VDD-2V; HCSL 50Ω to GND).

Key Specs (quick snapshot)

Typical test reference: 25±5°C, RH 40%–70% (unless otherwise specified by option).


Item	Value	Notes
Supply Voltage	LVPECL: 3.3V / 2.5V LVDS/HCSL: 3.3V / 2.5V / 1.8V	Per output format
Phase Noise (typ)	-150 dBc/Hz @10kHz -155 dBc/Hz @100kHz -160 dBc/Hz @1MHz	Example condition: 3.3V, 156.25MHz
Duty Cycle	45–55%	TH/T
Aging	±3 ppm/yr	1st year @25°C

If your platform has strict jitter budgets (PCIe / SerDes / optical), specify output format + VDD + frequency together for the RFQ.

Applications

Networking & Transport

40Gbit/100Gbit Ethernet, MAN
SONET / SDH, Fiber Channel
Line cards, switch ASIC reference clocks, optical modules

Why this spec matters: low integrated jitter improves timing margin for high-speed SERDES/PLL blocks and reduces link instability under noise coupling.

Instrumentation & Lab Systems

Test instrumentation and timing subsystems
Clock distribution trees where integrated jitter is critical
PLL reference and high-speed serializer clocking

Why this spec matters: predictable phase noise helps maintain measurement repeatability and reduces spurs across clock trees and synthesizers.

Detailed Specifications

LVPECL (3.3V / 2.5V)

LVPECL electrical characteristics
Parameter	Symbol	3.3V		2.5V		Units	Notes
		Min	Max	Min	Max
Frequency Range	F	100–220				MHz	Typical test: 25±5°C, RH 40%–70%
Standard Frequency	F(ST)	100, 125, 156.25				MHz
Supply Current	Icc	— / 65		— / 65		mA
Rise Time	Tr	— / 0.4		— / 0.4		ns	Measured 20%–80%
Fall Time	Tf	— / 0.4		— / 0.4		ns	Measured 20%–80%
Output High	VoH	2.215	2.42	1.415	1.64	V	Output High
Output Low	VoL	1.49	1.68	0.69	0.88	V	Output Low
Tri-State Enable	VIH	70% Vdd		70% Vdd		V	Enable
Tri-State Disable	VIL	30% Vdd		30% Vdd		V	Disable
Phase Noise (typ)	PN	-150 @10kHz / -155 @100kHz / -160 @1MHz				dBc/Hz	Example: 3.3V, 156.25MHz
Duty Cycle	TH/T	45–55				%
Standby Current	Icc(ST)	Max 30				µA
Start-up Time	Tosc	Max 5				ms
Aging	ppm/yr	±3				ppm/yr	1st year @25°C

Layout: place a 0.1µF bypass capacitor as close as possible between VDD and GND pads to preserve phase noise/jitter.

LVDS (3.3V / 2.5V / 1.8V)

LVDS electrical characteristics
Parameter	Symbol	3.3V		2.5V		1.8V		Units	Notes
		Min	Max	Min	Max	Min	Max
Frequency Range	F	100–175						MHz	Typical test: 25±5°C, RH 40%–70%
Standard Frequency	F(ST)	100, 125, 156.25						MHz
Supply Current	Icc	— / 35		— / 35		— / 25		mA
Rise Time	Tr	— / 0.3		— / 0.3		— / 0.4		ns	Measured 20%–80%
Fall Time	Tf	— / 0.3		— / 0.3		— / 0.4		ns	Measured 20%–80%
Differential Output Voltage	Vdiff	0.24	0.45	0.24	0.45	0.24	0.45	V	VOD, OUT–OUTN
Tri-State Enable	VIH	70% Vdd		70% Vdd		70% Vdd		V	Enable
Tri-State Disable	VIL	30% Vdd		30% Vdd		30% Vdd		V	Disable
Duty Cycle	TH/T	45–55						%
Standby Current	Icc(ST)	Max 30						µA
Output Load	RL	100Ω (between OUT & OUTN)						Ω	Typical LVDS termination
Start-up Time	Tosc	— / 5		— / 5		— / 5		ms
Aging	ppm/yr	±3						ppm/yr	1st year @25°C

LVDS termination: 100Ω between OUT and OUTN. Place a 0.1µF bypass capacitor close to VDD/GND pads.

HCSL (3.3V / 2.5V / 1.8V)

HCSL electrical characteristics
Parameter	Symbol	3.3V		2.5V		1.8V		Units	Notes
		Min	Max	Min	Max	Min	Max
Frequency Range	F	100–135						MHz	Typical test: 25±5°C, RH 40%–70%
Standard Frequency	F(ST)	100, 125						MHz
Supply Current	Icc	— / 46		— / 46		— / 46		mA
Rise Time	Tr	— / 0.6		— / 0.6		— / 0.6		ns	Measured 20%–80%
Fall Time	Tf	— / 0.6		— / 0.6		— / 0.6		ns	Measured 20%–80%
Output High	VoH	0.6	0.9	0.6	0.9	0.5	1.0	V
Output Low	VoL	-0.15	0.15	-0.15	0.15	-0.15	0.15	V
Tri-State Enable	VIH	70% Vdd		70% Vdd		70% Vdd		V	Enable
Tri-State Disable	VIL	30% Vdd		30% Vdd		30% Vdd		V	Disable
Duty Cycle	TH/T	45–55						%
Standby Current	Icc(ST)	Max 30						µA
Output Load	RL	50Ω to GND						Ω	Typical HCSL termination
Start-up Time	Tosc	— / 5		— / 5		— / 5		ms
Aging	ppm/yr	±3						ppm/yr	1st year @25°C

HCSL termination: 50Ω to GND. Place a 0.1µF bypass capacitor close to VDD/GND pads.

Package Outline & Frequency Stability

Package Outline & Recommended PCB Land Pattern

Package outline and recommended PCB land pattern (3.2×2.5mm)

Pin Function (reference)


Pin	Function	Notes
1	Tri-State / NC	Enable/Disable (per ordering option)
2	Tri-State / NC	Enable/Disable (per ordering option)
3	GND	Ground
4	OUT	Differential output
5	OUTN / NC	Differential output (option dependent)
6	VDD	Supply voltage

Note: Pin naming/behavior can vary by option. Confirm the final pin map when placing an order.

Board-level reminder: place a 0.1µF bypass capacitor close to VDD/GND pads; keep the return path short.

Frequency Stability vs. Temperature Range

Stability options by temperature band
Temp. Range	±20ppm	±25ppm	±50ppm
−20 to +70°C	○	○	○
−40 to +85°C	△	○	○
−40 to +105°C	×	×	○
−40 to +125°C	×	×	△

○: Available △: Conditional ×: Not available
Stability typically includes calibration @25°C, operating temperature range, input voltage variation, load variation, aging (1st year), shock, and vibration.

How to specify stability correctly

Specify temperature range and stability (ppm) together (e.g., −40~+85°C, ±25ppm).
If your system is sensitive to jitter/phase noise, also include the required output format, VDD, and frequency (e.g., 156.25MHz).
For non-standard frequencies or tighter stability, contact FCom Fuji Crystal for feasibility and lead time.

Ordering Code / Options

How to Specify

Model: FCO-3L-UJ
Output: LVPECL / LVDS / HCSL
VDD: 3.3V / 2.5V / 1.8V (per output)
Frequency: standard (100/125/156.25MHz) or custom within range
Temp Range & Stability: e.g., −40~+85°C, ±25ppm
Tri-state: Enable/Disable option (confirm pin behavior)

For custom frequencies, extended temperature, or special performance requirements, contact sales for feasibility and lead time.

Selection Path / Upgrade Options:
Need a smaller footprint? Consider FCO-2L-UJ (low jitter). Need more board margin or different platform matching? Consider FCO-5L-UJ (low jitter) or FCO-3L-PG-LVDS. For system-level matching, see Differential Oscillator Selection Guide for Optical Modules.

Request Quote / Sample Template

FCO-3L-UJ / Output: LVDS / VDD: 3.3V / Freq: 156.25MHz / Temp: −40~+85°C / Stability: ±25ppm / Qty: ____ pcs / Application: 100G Ethernet

Email: FCom@fujicrystal.com

Contact page: https://www.fujicrystal.com/contact.html

Downloads

Datasheet

FCO-3L-UJ Ultra-Low Jitter Differential Output Oscillator (PDF)

If you need specific test conditions, compliance notes, or platform jitter budgeting support, include it in your RFQ.

Platform Guides (internal)

Selection Path / Upgrade Options

Related differential oscillator options
Model	Package	Output	Positioning
FCO-2L-UJ (Low Jitter)	2.5×2.0mm	LVPECL / LVDS / HCSL	Smaller footprint option for low-jitter differential clocking
FCO-3L	3.2×2.5mm	LVPECL / LVDS / HCSL	General compact differential oscillator family footprint
FCO-3L-PG-LVDS	3.2×2.5mm	LVDS	Platform-focused LVDS option when LVDS-only clock trees are preferred
FCO-5L-UJ (Low Jitter)	5.0×3.2mm	LVPECL / LVDS / HCSL	More board margin with low-jitter differential outputs
Differential Output Oscillators	—	—	Browse the full differential oscillator portfolio

Knowledge links: What Is LVDS? · HCSL Crystal Oscillators – Practical Design Guide

FAQ

What frequency ranges are supported by FCO-3L-UJ?

LVPECL supports 100–220MHz, LVDS supports 100–175MHz, and HCSL supports 100–135MHz. Common standard frequencies include 100MHz, 125MHz, and 156.25MHz depending on output.

How do I preserve low jitter on the PCB?

Use the recommended land pattern, place a 0.1µF bypass capacitor as close as possible between VDD and GND pads, route the differential pair with controlled impedance and tight coupling, and keep away from switching noise sources.

What stability options are available across temperature range?

Common options include ±20/±25/±50ppm with availability depending on temperature range. The stability matrix indicates availability/conditional by temperature band; contact FCom Fuji Crystal for special requirements.

Do you publish pricing? How can I get a quotation?

We do not publish fixed pricing because it depends on frequency, output format, stability, temperature grade, and volume. Send your requirements and quantity for an RFQ.

What are typical MOQ, lead time, and sample options?

MOQ and lead time vary by option and frequency. Samples are available for evaluation, and volume production is supported after approval. Contact us with your target frequency, output, VDD, temperature range, and quantity.

Can you support customization and test/report requests?

Yes. We support custom frequencies within range, output option matching, and special requirements depending on feasibility. Test conditions or report requests can be discussed during the RFQ stage.

Support & Quality

Technical Support

Application engineering support for platform matching (output format, termination, routing, jitter budgeting)
Contact: Fcom@fujicrystal.com · Support入口

Tip: include platform/chipset, required output (LVDS/LVPECL/HCSL), frequency, VDD, temperature grade, and quantity for the fastest RFQ.

Certifications

Test-condition note: tables above reference typical conditions unless option-specific requirements are specified in the order.