Integrated RMS jitter <0.8 ps (12 kHz–20 MHz) for tight Ethernet/broadcast jitter budgets.

10–250 MHz output range. Control voltage range recommended: 0.3–3.0 V (center near mid-rail at 3.3 V).

Total stability ±20 ppm (cal + temp + aging + supply/load). Supply options 3.3 V / 2.5 V.

• Package size: 5.0 × 3.2 × 1.1 mm (6-pad SMD)
• Frequency range: 10 – 250 MHz (CMOS)
• Integrated jitter: <0.8 ps RMS (12 kHz – 20 MHz)
• Stability: ±20 ppm (cal + temp + aging + supply/load)
• Supply options: 3.3 V / 2.5 V
• Enable control: Tri-state output, clean start/stop

Measurement unless stated: V_DD=3.3 V, 25 °C, 15 pF load, representative F_o.

Engineer insights

• CMOS swing eases direct drive of SoC/FPGA pins, reducing level-translation parts.
• Small footprint helps replace larger 7×5 parts without routing congestion.
• Low close-in PN supports Ethernet PHY clocking and video timing where wander/jitter budgets are tight. See IEEE 802.3 guidance and oscillator applications in electronics.
• Choosing between XO/TCXO/OCXO? Read TCXO vs OCXO and Crystal vs MEMS oscillators.
• If your design targets comms sync/PLL timing, use the VCXO family hub: VCXO family for communication sync.

• Ethernet PHY / Switch clocks (25/50/125 MHz families) — IEEE 802.3
• Broadcast video timing trees (27 MHz, 74.25 MHz multiples) — SMPTE
• FPGA / SoC clock distribution — see selecting timing crystals
• General networking devices — networking & storage timing

Recommended Frequencies

Need a non-listed F_o? Custom options available.

More application notes

• WLAN / WiMAX timing — pair with IEEE 802.11
• Oscillators in 5G & telecom
• Industrial automation & robotics timing
• Wearable electronics timing & mobile phone timing
• TCXO for GNSS modules (when tighter temp stability is required)

Knowledge hub

• Frequency & crystal science
• How crystal oscillators work
• Why timing crystals matter
• Crystal vs MEMS oscillators
• Crystal oscillators for GNSS/GPS
• XTAL parameters & logic families

Unless noted: V_DD=3.3 V, 25 °C, 15 pF load.

PR / APR & Control

• PR (Pull Range): tunable window at reference conditions.
• APR (Absolute Pull Range): PR minus drifts (temp, load/supply, aging) — margin for design.
• Control V: 0.3–3.0 V recommended tuning range; center ~ mid-rail at 3.3 V.
• Linearity: ~10% typical around V_center.

Kvco (ppm/V) available per frequency option on request for loop design. Also see how to select timing parts.

Application notes

• Decoupling: 0.1 µF (X7R) close to VDD-GND + 1 µF bulk nearby. Keep return paths short.
• Control-voltage filter: If the loop allows, RC (e.g., 10 kΩ + 0.1 µF) to reduce ripple on V_c.
• Drive & loading: Budget for 15 pF CMOS load; buffer long traces/fan-out.
• Enable pin: Ensure deterministic tri-state at reset/boot; VIH/VIL as per table.
• Routing: Keep clock nets short; avoid stubs and plane-split crossings; consider guard traces.
• EMI: Isolate clocks from high dI/dt nodes; minimize loop areas and via count.

Validation checklist

• Jitter integration band matches component specs (12 kHz–20 MHz)
• PLL loop bandwidth and peaking verified with VCO noise model
• Supply noise (PSRR) impact checked at harmonics of switching rails
• Thermal drift corner runs across operating range
• XO aging margin added to APR for lifetime

Background: How crystal oscillators work • frequency & crystal science

Availability & Lead Time

*Actual stock/lead time varies by lot and region. Ask for current availability when sending RFQ.

MOQ & Pricing Drivers

• MOQ: Flexible; engineering samples available for validation.
• Price breaks: Common at higher volumes (e.g., 1k/10k/50k+).
• Cost drivers: Frequency option, stability/temp, PR/APR target, screening, packaging.
• Speed your quote: Include F_o, stability/temp, PR/APR, supply/load, est. annual volume, target lead time.

Quick RFQ Email

Trade & Logistics

• Incoterms: Standard terms (e.g., EXW/FOB/DDP) supported — confirm on quotation/PI.
• Packaging: Tape & Reel (EIA-481), moisture level MSL 1, JEDEC reflow compatible.
• Documentation pack: RoHS/REACH declarations, material info, label/traceability on request (EU RoHS, ECHA REACH).
• After-sales: Failure-analysis support and RMA process available per FCom terms.

Need distributor or local invoicing? Email FCom@fujicrystal.com for regional options.

Onboarding & AVL

• Company details & tax info for PI
• Requested PN/marking format & packaging
• Quality/Compliance docs for AVL approval

Sample → MP Path

1. RFQ & technical confirmation
2. Samples for validation
3. NPI ramp (pilot)
4. Mass production scheduling

Timelines depend on frequency and options — confirm when ordering.

What to specify

• Frequency (e.g., 25.000000 / 125.000000 MHz)
• Stability class & temperature range (aim APR)
• Supply (2.5 V / 3.3 V), output load (CMOS 15 pF)
• PR/APR target and desired Kvco behavior
• Enable polarity & packaging (Tape & Reel)

More guidance: Selecting the right timing crystal/oscillator.

Datasheet & CAD

Request Datasheet

Request CAD

Compliance

RoHS/REACH declarations available. MSL handling per JEDEC.

EU RoHS • ECHA REACH • JEDEC

Ordering Code / Options

• Frequency (F_o): 10–250 MHz (specify exact frequency)
• Output: CMOS (single-ended)
• Supply: 3.3 V / 2.5 V
• Temperature grade: -40 to +85 °C (ask for extended options if needed)
• Control: PR/APR target + preferred Kvco (ppm/V)
• Packaging: Tape & Reel

Selection Path / Upgrade Options: If you need tighter EMI or longer routes/high fan-out, consider differential VCXO: FVC-5L-PG (LVPECL/LVDS). For comms sync and PLL timing workflows, use VCXO family hub and the engineering guide.

Documents & Downloads

Package outline image (for documentation/AVL). For the latest FVC-5P-LJ datasheet, use “Request Datasheet”.

Reference datasheet (differential FASTVCXO family, related option): FVC-5L-PG differential FASTVCXO datasheet (PDF)

Need test reports (jitter/PN curves), MSL/reflow, or compliance pack? Email FCom@fujicrystal.com.

Can FVC-5P-LJ replace a differential VCXO?

In many low-noise systems using CMOS receivers, yes. For long routes/high fan-out or tight EMI, consider differential options like FVC-5L-PG.

Supply options?

Available in 3.3 V and 2.5 V variants. Keep the rail clean; LDO + local decoupling recommended.

PR vs APR?

PR is the tuning window at reference conditions. APR subtracts worst-case drifts (temp, load/supply, aging) and is what your design must meet across life.

Typical load / symmetry / edges?

CMOS 15 pF typical; duty cycle 45–55% (typ); rise/fall <5 ns (typ), frequency & load dependent.

Center V_c and Kvco?

Center control ≈ mid-rail at 3.3 V. Kvco (ppm/V) varies by F_o; contact us for per-frequency data.

Samples & quote?

Yes. Provide F_o, stability/temp, PR/APR target, supply/load, and annual volume for a fast quotation.

Why is there no public price listed?

This is a B2B timing component with multiple frequency/options and screening choices. We quote based on your F_o, stability, PR/APR, and volume. Request RFQ for a fast response.

What is the MOQ?

We support small-quantity engineering samples and flexible MP MOQs depending on options. Include your ramp plan in the RFQ for best pricing.

How long is the lead time?

Popular frequencies are often available faster via standard builds; custom options are build-to-order. We will confirm current lead time on the quotation/PI.

Which shipping and Incoterms are supported?

We work with standard Incoterms (e.g., EXW/FOB/DDP) and major couriers. Your regional sales contact will confirm on the quote.

What compliance documents can you provide?

RoHS/REACH declarations, material information for customer approval processes, and MSL/reflow data per JEDEC. See also why timing crystals matter.

Do you support customization?

Yes. Frequency, control range/Kvco targets, and screening options can be tailored. Share your PLL/jitter budget and constraints in the RFQ.