FVC-5L-PG VCXO 5.0×3.2mm LVPECL/LVDS 10–1500MHz
SMD 5.0×3.2mm, FASTVCXO
FEATURE
Product Description
FVC-5L-PG – 5.0×3.2 mm Differential Output VCXO – FASTVCXO (LVPECL/LVDS)
High-frequency differential VCXO for telecom synchronization, clock cleaners/jitter attenuators, and high-speed data paths. ≤1 ps RMS jitter and ±50 ppm APR help improve PLL lock margin and system timing stability. Samples, volume supply and customization are available on request.
Overview
FVC-5L-PG is a compact 5.0×3.2 mm differential VCXO (FASTVCXO) delivering 10–1500 MHz with ≤1 ps RMS jitter and ±50 ppm APR (option). It provides clean clocks for PLLs, jitter attenuators, clock cleaners and high-speed links in telecom synchronization, gateways, and advanced mixed-signal systems.
For VCXO timing in communication synchronization and PLL design, see: VCXO for communication sync & PLL timing, the engineering guide, and the VCXO family overview.
For a broader overview of timing devices, see our article What Are Timing Devices? and What is an Oscillator?
Tape & Reel (EIA-481) RoHS/REACH declaration available Customization on request
Key Features
- Package: 5.0 × 3.2 mm ceramic SMD (differential clock module)
- Frequency: 10 MHz to 1500 MHz (option dependent)
- Output: Differential LVPECL / LVDS (select per system interface)
- Absolute Pull Range (APR): ±50 ppm (option); PR/APR depends on stability and conditions
- Control voltage: 0.3–3.0 V (Vcenter ≈ Vdd/2; linearity depends on option)
- RMS phase jitter: ≤1 ps (12 kHz to 20 MHz, typ., option dependent) [ITU-T G.8261 (sync concepts)]
- Phase noise @614.4 MHz: –105 dBc/Hz @10 kHz offset (typ.)
- Tri-state enable/disable, differential termination per LVPECL/LVDS practice
- Operating temperature: –20 to +70 ℃ (options available)
Key Specs
Typical test conditions (unless noted): Vdd=3.3 V, 25 ℃, differential termination per interface, Fo=614.4 MHz.
Clock Quality
- RMS phase jitter: ≤1 ps (12 kHz–20 MHz, typ., option dependent)
- Phase noise: –105 dBc/Hz @10 kHz offset (614.4 MHz, typ.)
- Differential output: LVPECL / LVDS
- Rise/Fall: ≤ 1.0 ns (typ., depends on Fo and output)
Tuning & Operating
- Frequency range: 10–1500 MHz (option dependent)
- APR: ±50 ppm (option)
- Control voltage: 0.3–3.0 V (Vcenter ≈ Vdd/2)
- Temperature: –20 to +70 ℃ (options available)
- Enable: tri-state output control
Typical Applications
Recommended Frequencies (examples)
| Application | Typical Fo | Notes |
|---|---|---|
| Telecom sync / transport | 122.88 / 125 / 155.52 / 200 MHz | Common sync and line-rate related clocks |
| Clock cleaners / jitter attenuators | 491.52 / 622.08 MHz | Higher-rate clock domains; option dependent |
| High-speed ADC/DAC & SERDES | 100–1500 MHz | Interface and sampling clocks; depends on output standard |
| Networking / gateways | 125 / 156.25 MHz | Ethernet-related clocks (example) |
Exact frequency/output options depend on availability and interface; contact FCom for custom Fo.
Design Guide
Application Circuit (Differential)
- Decoupling: Place 0.1 μF (X7R) + 1 μF close to Vdd. Keep return paths short.
- Control voltage filtering: RC low-pass (e.g., 10 kΩ + 0.1 μF) from DAC/loop filter to pin; minimize ripple.
- Termination: Use proper differential termination (e.g., 100 Ω across the pair for LVDS; LVPECL per receiver/AC-coupling guidelines).
- Routing: Route as a differential pair with controlled impedance; length-match and avoid stubs.
- Enable (tri-state): VIH ≥ 0.7×Vdd, VIL ≤ 0.3×Vdd (logic relative to Vdd).
- Power: Clean, low-noise rail (2.5 V / 3.3 V option). Consider LDO + ferrite bead if shared with PLL/PHY.
See also: How crystal oscillators work, Selecting a timing crystal.
Measurement conditions (unless noted): Vdd=3.3 V, 25 ℃, differential termination per interface.
Tuning & Stability
- PR vs APR: PR = tunable window at reference; APR considers temp/aging/load/supply.
- Vcenter: ~Vdd/2. Keep control within 0.3–3.0 V for linear region (option dependent).
- Kvco (ppm/V): Provided per Fo on request for loop design and margining.
- Stability grade: Options available; choose based on APR requirement and environment.
- Aging: Allocate margin for lifetime drift per program requirement.
Reflow & MSL guidance: JEDEC J-STD-020, JEDEC J-STD-033.
Electrical Specifications
| Parameter | Value | Unit |
|---|---|---|
| Frequency Range | 10 ~ 1500 (option dependent) | MHz |
| Supply Voltage | 2.5 / 3.3 (option dependent) | V |
| Control Voltage | 0.3 ~ 3.0 (Vcenter ≈ Vdd/2) | V |
| Output Type | Differential (LVPECL / LVDS) | — |
| Absolute Pull Range (APR) | ±50 (option) | ppm |
| RMS Phase Jitter (12 kHz–20 MHz) | ≤ 1 (typ., option dependent) | ps |
| Phase Noise (example) | –105 @10 kHz (Fo=614.4 MHz, typ.) | dBc/Hz |
| Rise / Fall Time | ≤ 1.0 (typ., depends on Fo and output) | ns |
| Supply Current (typ.) | Depends on Fo and output standard | mA |
| Operating Temperature | –20 to +70 (options available) | °C |
| Storage Temperature | –55 to +125 | °C |
| Start-up Time | ≤ 10 (typ., option dependent) | ms |
| Tri-state Input VIH / VIL | 0.7×Vdd / 0.3×Vdd | V |
| Reflow / MSL | 260 °C 10 s / MSL 1 | — |
| Notes | Unless noted: Vdd=3.3 V, 25 °C, differential termination per interface | — |
* APR/PR and Kvco are option dependent and vary with temperature, load and supply variations. Contact FCom for APR and Kvco (ppm/V) options.
Compare with Similar Models
| Model | Size (mm) | Output | Max Frequency | Positioning | Target Applications |
|---|---|---|---|---|---|
| FVC-5P-LJ | 5.0×3.2 | Differential (LVPECL / LVDS) | 170 MHz | Ultra-Low Jitter | 5G / Data Center / Sync |
| FVC-5X | 5.0×3.2 | CMOS | 170 MHz | Cost-effective | Consumer, WLAN, VoIP |
| FVC-5L-PG | 5.0×3.2 | Differential (LVPECL / LVDS) | 1500 MHz | Telecom-grade FASTVCXO | Clock cleaners / SDH / SONET / Sync |
Ordering Information & Part Numbering
How to specify
- Frequency (Fo) — e.g., 122.880000 MHz, 155.520000 MHz, 622.080000 MHz
- Stability grade / Temp range — target APR across your environment
- Supply / Output / Termination — 2.5V or 3.3V, LVPECL or LVDS, receiver/termination details
- APR/PR target / Kvco — ±50 ppm APR (option), Kvco as needed for PLL design
- Enable polarity / Packaging — tri-state enable, Tape & Reel
- Documentation — compliance declarations if required
Providing the above in your RFQ shortens lead time and ensures optimal APR margining.
Selection Path / Upgrade Options: If you need tighter PLL margin, sync timing guidance, or family comparison, review VCXO family (communication sync), the VCXO engineering guide, and the knowledge note VCXO sync & PLL timing.
Part Number Format (example)
| Field | Code | Example |
|---|---|---|
| Series | FVC-5L-PG | FVC-5L-PG |
| Frequency | Fo in MHz | 155.520 |
| Stability/Temp | Option grade | F/Y |
| Supply/Output | 2V5/3V3 + P/L | 33P |
| APR/Option | APR50 | 50 |
| Packaging | TR | TR |
Part-marking and full code legend available upon request.
Documents & Downloads
Datasheet
Download FVC-5L-PG Differential VCXO Datasheet (PDF)
Tip: Include Fo, stability/temperature range, APR/PR target, output type and termination in your RFQ to speed up quotation.
Package Outline
Package outline
Quality, Compliance & Logistics
- Compliance: RoHS/REACH declarations available on request (lead-free). [EU RoHS] [ECHA REACH]
- Reliability: Screening and reliability test reports can be provided for approval.
- Packaging: Tape & Reel per EIA-481; moisture sensitivity MSL 1.
- Samples: Engineering samples available for validation.
- Customization: Frequency options, APR/PR targets, and Kvco tuning on request.
- Certifications: ISO 9001, ISO 14001
Fast RFQ Template
Click to open email with a pre-filled template:
Alternatively, email Fcom@fujicrystal.com or use technical support / application engineering to share your PLL and synchronization requirements.
Frequently Asked Questions
Q1: Can FVC-5L-PG operate up to 1500 MHz?
Yes. It supports high-frequency differential outputs up to 1500 MHz (option dependent).
Q2: Which output standards are supported?
Differential LVPECL and LVDS outputs are supported. Specify your interface in the RFQ.
Q3: Does it support tri-state output control?
Yes. The VCXO supports tri-state enable/disable via the enable pin.
Q4: What’s the difference between Pull Range (PR) and APR?
PR is the tunable range under reference conditions; APR additionally accounts for temperature, load and supply variations, and aging, and depends on the selected stability grade and application conditions.
Q5: What is the center control voltage and tuning sensitivity (ppm/V)?
The center control voltage is approximately mid-rail (Vdd/2). Tuning sensitivity (Kvco, ppm/V) varies with frequency and option; contact FCom for loop-design data.
Q6: Do you provide samples and quotes?
Yes. Provide frequency, stability/temperature range, output type, termination/load, APR/PR target, supply, and annual volume to receive a fast quote and lead-time recommendation.
Q7: Is it RoHS/REACH compliant?
RoHS/REACH compliance declarations and material information are available for customer approval processes.
Q8: What are MOQ and lead time for FVC-5L-PG?
MOQ and lead time depend on the selected frequency/output and stability grade. Share your target Fo, APR/PR, and quantity, and we will recommend a supply plan for sampling and volume production.
Q9: Can you customize frequency, APR/PR targets, or output options?
Yes. Frequency options, APR/PR targets, tuning characteristics, and output configurations can be customized for your PLL and synchronization needs. Contact FCom with your system requirements.
Order & Inquiry
Contact: Fcom@fujicrystal.com
- Email subject: “FVC-5L-PG Sample / RFQ”
- Include: Frequency, stability/temperature, APR/PR, output type, termination/load, supply, enable option, packaging, annual volume
- We support customization and provide compliance documents upon request
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