What is the jitter performance of FVC-3P-LJ?

Typical RMS jitter is 0.6 ps in Integer mode and 0.8 ps in Fractional mode, integrated from 12 kHz to 20 MHz.

What is the control voltage and pull range?

Control voltage range is 0.3–3.0 V (center ~1.65 V at 3.3 V). Pull (APR) options are ±50 ppm or ±150 ppm.

Does it support enable/disable?

Yes. Tri-state via Pin-2 (VIH ≥ 70% VDD, VIL ≤ 30% VDD).

FVC-3P-LJ — Low Jitter FASTVCXO (10–250 MHz, 3.2×2.5 mm, CMOS)

Q: Do you provide samples and what is the MOQ?

Yes—samples are available for evaluation. MOQ depends on frequency/configuration; send an RFQ with your target frequency, APR, and quantity.

Q: What is the lead time for production?

Lead time varies by frequency, APR option, and order size. Contact us with your requirements for the latest schedule.

Q: Can you customize frequency/options or provide test reports?

Yes—custom frequencies and configuration support are available. Compliance/testing documentation (e.g., RoHS/REACH, performance data) can be provided on request.

Q: Why is there no public price listed?

This is a B2B product. Pricing depends on frequency, configuration, volume, and delivery terms—please request a quote (RFQ).

10–250 MHz • 0.6 ps typ RMS jitter (12 kHz–20 MHz) • ±50/±150 ppm APR • Tri-state enable

Positioning: a compact, ultra-low jitter VCXO for server/networking clock trees, PLL-based sync modules, and FPGA/SerDes references where margin is tight and pull range matters.

Compact 3.2×2.5 mm footprint for dense networking & compute boards
Ultra-low jitter for SerDes/FPGA clocking and GbE/SONET/SDH links
Flexible APR options (±50/±150 ppm) to close PLL loop budgets

📩 Get Quote / Sample 👨‍💻 Talk to an Engineer 📄 Request Datasheet 🧾 Contact / RFQ

CMOS Output 3.3 V / 2.5 V APR ±50 / ±150 ppm Tri-state 3.2×2.5 mm

Overview

FVC-3P-LJ is a compact 3.2×2.5 mm VCXO delivering 10–250 MHz CMOS output with ultra-low RMS jitter (0.6 ps typ., 12 kHz–20 MHz). With ±50/±150 ppm APR options, 3.3 V/2.5 V supply, and tri-state enable, it suits GbE/SONET/SDH, Fibre Channel, enterprise servers, and FPGA/SerDes clocking. Explore our broader timing devices guide.

VCXO in PLL timing (recommended): read the engineering guide, the related news/insights, and the VCXO family page for comm-sync applications.

Why Engineers Choose FVC-3P-LJ

Ultra-Low Jitter Clock

0.6 ps typ RMS jitter (12 kHz–20 MHz) helps maintain link margins in high-speed SerDes and reduces downstream TX/RX jitter tax.

Small, Power-Friendly

3.2×2.5 mm package fits dense NICs and switches; CMOS output simplifies routing and reduces power vs. differential drivers when appropriate.

Flexible Pull Range

±50/±150 ppm APR options provide headroom for PLL tuning, temperature drift compensation, and manufacturing tolerances.

Key Features

Compact SMD package: 3.2 × 2.5 mm
Frequency range: 10 – 250 MHz
Very low phase jitter (12 kHz–20 MHz): 0.6 ps typ (Integer), 0.8 ps typ (Fractional) (RMS jitter calc.)
Phase noise (typ, 250 MHz @ 3.3 V): −107 dBc/Hz (1 kHz), −111 (10 kHz), −114 (100 kHz), −125 (1 MHz), −147 (20 MHz)
Supply options: 3.3 V / 2.5 V; ICC ≤ 50 mA @3.3 V (≤ 45 mA @2.5 V)
Control voltage (Vc): 0.3 – 3.0 V (center ~1.65 V @3.3 V / ~1.25 V @2.5 V)
Pull range (APR): ±50 ppm or ±150 ppm (options)
Tri-state enable via Pin-2; start-up time ≤ 10 ms

Specifications

Key Specs (At-a-Glance)

Typical values unless noted (e.g., 25 °C, stated VDD, and RMS jitter integrated 12 kHz–20 MHz). Verify in-circuit for your frequency/load/PLL conditions.

Frequency

10–250 MHz

CMOS output

RMS Jitter

0.6 ps typ

Integer (12 kHz–20 MHz)

Pull Range (APR)

±50 / ±150 ppm

Option dependent

Package

3.2×2.5 mm

SMD

Supply

3.3 V / 2.5 V

≤50 mA @3.3 V

Enable

Tri-state

Pin-2 control

Detailed Specifications (Electrical)

Electrical Specifications — FVC-3P-LJ
Parameter	3.3 V	2.5 V	Unit	Notes
Frequency Range	10 – 250		MHz
Supply Current (CMOS)	≤ 50	≤ 45	mA
Rise / Fall Time	≤ 3.0 / ≤ 3.0	≤ 3.0 / ≤ 3.0	ns	10–90%
Output Levels (VOH / VOL)	≥ 2.97 / ≤ 0.33	≥ 2.25 / ≤ 0.25	V	CMOS, device level
Duty Cycle	45 – 55		%
Tri-state (Pin-2)	VIH ≥ 70% VDD, VIL ≤ 30% VDD		—	Enable/Disable
Standby Current	≤ 18		µA
Load Capacitance	15 pF (≤200 MHz), 5 pF (200–250 MHz)		—	Typical
Start-up Time	≤ 10		ms
Control Voltage (Vc)	0.3 – 3.0 (center ~1.65)	0.25 – 2.25 (center ~1.25)	V	Pin-1
APR (Pull Range)	±50 ppm / ±150 ppm (options)		ppm	Linearity 5–10%, Mod BW ~10 kHz
VC Input Impedance	≈ 1		MΩ
RMS Jitter (12 kHz–20 MHz)	0.6 ps typ (Integer), 0.8 ps typ (Fractional)		ps	See note below
Phase Noise (typ., 250 MHz)	−107 dBc/Hz (1 kHz), −111 (10 kHz), −114 (100 kHz), −125 (1 MHz), −147 (20 MHz)		dBc/Hz	About phase noise

Notes: Electrical data at 25 °C, VDD as stated, unless noted. Jitter and phase noise are typical and vary with frequency, loading, and PCB design. Place a 0.1 µF bypass capacitor close to VDD–GND; for Vc, an RC (e.g., 10 kΩ + 0.1 µF) can improve tuning stability (verify in-circuit).

Applications

High-speed Gigabit Ethernet, SONET/SDH
Fibre Channel, Storage Area Networks (SAS/SATA)
Enterprise servers and network switches
Microprocessors / DSP / FPGA clocking
Broadband access equipment and Smart Grid

Why these specs matter in real systems

SerDes / switch fabrics: low integrated jitter helps preserve UI margin and reduces clock-induced BER pressure.
PLL-based sync modules: APR range (±50/±150 ppm) provides tuning headroom to close loop budget across drift/tolerances.
Dense server boards: small 3.2×2.5 mm footprint and CMOS routing simplify implementation when differential clocks are not required.

Related application notes: Networking & storage • 5G telecom • Industrial automation & robotics • WLAN/WiMAX • Wearable electronics • Mobile phones • For GNSS timing with TCXO see TCXO for GNSS.

Ordering Code / Options

Core Options

Frequency: 10–250 MHz
Output: CMOS (single-ended)
Enable: Tri-state (Pin-2)

Electrical Options

Supply: 3.3 V / 2.5 V
APR: ±50 ppm / ±150 ppm
Control Vc: 0.3–3.0 V (3.3 V)

Program Notes

Tell us your PLL center voltage, tuning slope needs, and loop bandwidth.
Share load/trace details (CMOS edge rate vs SI).
Ask for sample + production schedule in the same RFQ.

Selection Path / Upgrade Options

If you are selecting VCXOs for communication sync & PLL timing, start with the VCXO family page, then use the engineering guide to match APR, noise, and topology. For context and updates, see VCXO communication sync insights.

Also compare: FVC-3L-PG (differential) • Knowledge: XTAL parameters • Basics: Timing devices

Compare Models: FVC-3P-LJ vs FVC-3L-PG

Feature	FVC-3P-LJ	FVC-3L-PG
Package Size	3.2 × 2.5 mm	3.2 × 2.5 mm
Output Type	CMOS (single-ended)	LVDS / LVPECL (differential)
Frequency Range	10 – 250 MHz	10 – 1500 MHz
RMS Jitter (12 kHz – 20 MHz)	0.6 ps typ / 0.8 ps typ	< 1 ps typ
Phase Noise (typ.)	@250 MHz: −107 (1 kHz), −111 (10 kHz), −114 (100 kHz), −125 (1 MHz), −147 (20 MHz) dBc/Hz	@614.4 MHz: −70 (100 Hz), −95 (1 kHz), −105 (10 kHz) dBc/Hz
Supply / Current	3.3 V / 2.5 V • ≤ 50 mA	3.3 V / 2.5 V • up to 100 mA (LVPECL)
Best For	Single-ended clock trees, cost/power sensitive	High-speed differential clock trees, SI margin

Rule of thumb: choose FVC-3P-LJ (CMOS) for single-ended clocks and lower power; choose FVC-3L-PG (LVDS/LVPECL) for high-speed differential clock trees and cleaner SI margins.

Design-in Checklist

Clock Budget

Required output frequency (MHz)
Total jitter budget (UI / ps)
APR need (±50 or ±150 ppm)

Electrical

Supply voltage: 3.3 V or 2.5 V
Load: 15 pF (≤200 MHz) / 5 pF (200–250 MHz)
Duty cycle target (45–55% typ)

Layout & Control

0.1 µF close to VDD–GND
Short, impedance-controlled trace
VC pin optional RC filter (e.g., 10 kΩ + 0.1 µF)

For a quick review, email us your clock tree diagram and constraints—we’ll help validate headroom and APR selection.

Downloads & Resources

Request Datasheet (PDF)

Get the full pinout, recommended reflow, and extended electrical tables.

📄 Request Datasheet

Learn the Fundamentals

Brush up on jitter & phase-noise budgeting and timing device selection.

XTAL jitter & phase-noise explainer • What are timing devices? • What is an oscillator in electronics?

Authoritative Concept Guides

External links open in a new tab for convenience.

FCom In-depth Guides

Frequently Asked Questions

Q1. What is the typical jitter?
0.6 ps RMS (Integer) and 0.8 ps RMS (Fractional), integrated from 12 kHz to 20 MHz. See ADI MT-008 for conversion from phase noise to jitter.

Q2. What pull range options are available?
±50 ppm or ±150 ppm APR via 0.3–3.0 V control voltage (center ~mid-rail). APR vs PR.

Q3. Does it support tri-state enable?
Yes. Pin-2 high (≥70% VDD) enables the output; low (≤30% VDD) disables it.

Q4. Do you provide samples and what is the MOQ?
Yes—samples are available for evaluation. MOQ depends on frequency/configuration; send an RFQ with your target frequency, APR, and quantity.

Q5. What is the lead time?
Lead time varies by frequency, APR option, and order size. Contact us with your requirements for the latest schedule.

Q6. Can you customize frequency/options or provide test reports?
Yes—custom frequencies and configuration support are available. Compliance/testing documentation (e.g., RoHS/REACH, performance data) can be provided on request.

Q7. Why is there no public price listed?
This is a B2B product. Pricing depends on frequency, configuration, volume, and delivery terms—please request a quote (RFQ).

Need fundamentals? See Downloads & Resources above for guides.

Order & Inquiry (RFQ)

Need a specific frequency or configuration? We support customization. Contact us for pricing, lead time, and samples.

Quick RFQ Template

Copy & fill the fields:

Model: FVC-3P-LJ
Frequency (MHz):
Supply (3.3V / 2.5V):
APR (±50 / ±150 ppm):
Qty & target date:
Ship-to country:
Application notes:

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Talk to an Engineer

Get guidance on APR selection, PLL loop margins, and layout tips.

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Adjacent Model

Need a differential output for high-speed links?

FVC-3L-PG (LVDS/LVPECL, 10–1500 MHz)

Compliance documentation (e.g., RoHS/REACH) available on request. Actual performance depends on frequency, load, and PCB implementation.

FVC-3P-LJ — Low-Jitter FASTVCXO (10–250 MHz)

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