FCO-2C-WT 2.5×2.0mm Wide-Temp Oscillator

Key Features

Wide temperature: options up to −55~+125°C with matched stability bins.
Low jitter: ≤1.0 ps RMS (12 kHz–20 MHz) for RF/SERDES/high-speed logic.
Flexible supply: 1.8 / 2.5 / 3.3 V CMOS (15 pF load).
Fast start: ≤2 ms start-up; 45–55% duty cycle.
Low power: ≤10 mA @ ≤80 MHz (typ), ≤15 mA above 80 MHz.
OE / Tri-state: Pin-1 enable for power budgeting and bus sharing.

Why these specs matter

Extended temperature reduces clock drift and prevents timing margin collapse in under-hood and harsh industrial cabinets.
Low RMS jitter protects SERDES eye opening and sampling margin in high-speed digital and RF front-ends.
OE tri-state enables standby power strategies and shared clock trees without extra buffering.

Need selection help? Use the RFQ to specify frequency, ppm bin, temperature grade, Vdd, and quantity so we can confirm feasibility and lead time.

Applications

FCO-2C-WT is designed for systems that must boot reliably and maintain tight timing margin across wide thermal excursions. Typical use cases include:

Oil & gas drilling / geothermal tools: high temperature soak, shock, and vibration.
Automotive ECU (under-hood): thermal cycling, cold crank noise, and long mission time.
Industrial instrumentation & control: PLCs, gateways, and remote I/O with noisy power rails.
Commercial space & aerospace: harsh thermal profile and reliability-focused BOM.
Extreme environment electronics: outdoor infrastructure and sealed enclosures.

Applications of FCO-2C-WT oscillator in oil drilling, aerospace, automotive and industrial instrumentation

Application-to-spec mapping

Boot + watchdog timing: fast start-up helps deterministic reset recovery and quick time-to-service.
High-speed interfaces: low RMS jitter improves margin for Ethernet/PCIe/FPGA clocks (system-dependent).
Noisy rails: robust decoupling practice keeps supply noise from modulating clock edges.
Wide thermal drift: choosing the correct ppm bin per temperature grade prevents “hidden” timing failures during thermal sweeps.

For architectural background, see Oscillator & Clock Applications, Networking & Storage Clocks, and Oscillators in 5G Telecom.

Detailed Specifications

Parameters	Symbol	Min.	Typ.	Max.	Unit	Notes
Frequency Range	F	1.25	—	100	MHz
Supply Voltage	Vdd	—	1.8 / 2.5 / 3.3	—	V	Nominal options
Current Consumption (≤80 MHz)	Icc	—	—	10	mA	Max
Current Consumption (>80 MHz)	Icc	—	—	15	mA	Max
Rise / Fall Time (10–90%)	Tr / Tf	—	—	5	ns	CL = 15 pF
Output Load	CL	—	15	—	pF	CMOS
Output High / Low	VoH / VoL	0.9×Vdd	—	0.1×Vdd	V	CMOS levels
Period Jitter (pk)	—	—	—	40	ps	Max
RMS Phase Jitter	PJ	—	0.2	1.0	ps	12 kHz–20 MHz
Duty Cycle	TH/T	45	—	55	%
Start-up Time	Tosc	—	—	2	ms	Max
Aging (first year @25°C)	—	—	—	±3	ppm/yr

Test conditions: 25 ± 5°C, 40–70% RH. Inclusive stability bins account for calibration @25°C, temperature range, supply and load variation, aging (1st year), shock and vibration.

Stability (ppm)	−40~+85°C	−40~+105°C	−40~+125°C	−55~+125°C
±30	Available	Conditional	Not available	Not available
±40	Available	Available	Not available	Not available
±50	Available	Available	Conditional	Not available
±100	Available	Available	Available	Available

Legend: Available Conditional Not available

Pin 1 (OE)	Threshold	Function
VIH	≥ 0.7 × Vdd	Output Enable
VIL	≤ 0.3 × Vdd	Output Disable (High-Z)

Design tip: place a 0.1 µF bypass capacitor close to Vdd–GND pads.

Mechanical & Footprint

Package: 2.5 × 2.0 mm SMD, industry-standard pad layout.
Output: CMOS, 15 pF load.
Pin-1: OE (tri-state), Pin-2: GND, Pin-3: OUT, Pin-4: Vdd.
Marking: Device code and lot ID (see datasheet drawing).

Ordering Code / Options

What to specify in an RFQ

Frequency: target MHz (1.25–100 MHz)
Stability bin: ±30 / ±40 / ±50 / ±100 ppm
Temperature grade: −40~+85°C / −40~+105°C / −40~+125°C / −55~+125°C
Supply voltage: 1.8 V / 2.5 V / 3.3 V
OE requirement: enable polarity and standby behavior
Quantity & packaging: prototypes vs volume

Supply options vary by frequency and temperature grade. If you need conditional bins (e.g., ±30 ppm at −40~+105°C), call it out in the RFQ.

Selection tips

Thermal margin first: pick the temperature grade that matches your worst-case enclosure/under-hood profile.
Then ppm: choose the stability bin that protects protocol timing/baud rate/MCU clock tolerance across temperature.
Then jitter: validate RMS jitter needs against your interface budget (SERDES/ADC/RF clocking).
Power & OE: use OE tri-state for standby strategy and clock tree sharing.

For fundamentals, see What Is a Clock Oscillator?, How Crystal Oscillators Work, and Key Oscillator Parameters.

Documents & Downloads

Datasheet (PDF): FCO-2C-WT wide temperature CMOS oscillator (2.5×2.0mm)
Wide-temperature oscillator overview: Wide Temperature Oscillators
Family landing pages: Crystal-Controlled Oscillator Guide

For compliance and management systems: ISO9001 and ISO14001.

Package / footprint reference

FCO-2C-WT CMOS oscillator package drawing (2.5×2.0 mm)

If you need a specific pad stack or solder profile alignment, include your PCB constraints in the RFQ.

Selection Path / Upgrade Options

FCO-2C

General-purpose CMOS • 1.25–125 MHz

View FCO-2C

FCO-2C-HP

High precision option • tighter stability bins

View FCO-2C-HP

FCO-2C-UP

Ultra-low power • 1–50 MHz

View FCO-2C-UP

FCO-2C-LE

Low-EMI (Spread-Spectrum) • 16–40 MHz

View FCO-2C-LE

If your system is sensitive to interference or emissions, consider the low-EMI option. If your priority is tighter frequency tolerance across temperature, evaluate the high-precision option. For power-limited designs, check the ultra-low-power variant.

Order & Inquiry

Tell us your required frequency, stability, temperature range, Vdd, and quantity. Our team will confirm lead time and pricing.

Technical support: application engineering can help review clock-tree placement, decoupling, OE behavior, and temperature/stability trade-offs for your design constraints.

FAQ

What frequency-stability options are available across the wider temperature ranges?

Standard options are ±30/±40/±50/±100 ppm. At −40~+85°C, all are available. At −40~+105°C, ±40/±50/±100 ppm are standard while ±30 ppm may be conditional. At −40~+125°C, ±100 ppm is standard and ±50 ppm may be conditional. At −55~+125°C only ±100 ppm is offered.

How should I decouple the supply for best jitter performance?

Place a 0.1 µF bypass capacitor as close as possible between Vdd and GND pads, and keep the return path short to reduce supply noise and clock edge distortion.

How is output enable/disable controlled (OE / tri-state)?

Pin 1 is OE/Standby. Drive high (≥0.7×Vdd) to enable output; drive low (≤0.3×Vdd) to tri-state the output.

Do you support samples and volume production?

Yes. We support sampling, volume production, and custom frequency/temperature/stability bins. Send your requirements (frequency, ppm, temp range, Vdd, quantity) for an RFQ.

What is the MOQ and typical lead time?

MOQ and lead time depend on frequency and temperature/stability option. Provide your target specs and quantity; we will confirm stock status and production schedule in the RFQ.

Can you customize output, temperature grade, or screening?

Yes. Custom frequency, voltage, stability bins, temperature grade (including extended range), and screening/reporting can be supported subject to feasibility review.

Can you provide test reports for harsh-environment programs?

On request, we can support program-specific documentation (e.g., temperature characterization and other verification reports) aligned to your qualification flow. Contact us with your test plan needs.