What is the typical RMS phase jitter of FCO‑6P‑PJ?

0.8 ps typical, measured over 12 kHz to 20 MHz at 50 MHz output. Integer‑mode maximum is 1.5 ps; fractional‑mode maximum is 2.0 ps.

Which supply voltages are supported?

1.8 V, 2.5 V, and 3.3 V. Logic thresholds for tri‑state control are VIH ≥ 0.7×VDD (Enable) and VIL ≤ 0.3×VDD (Disable).

How fast does the output start up?

The start‑up time is ≤8 ms.

What stability options and temperature ranges are offered?

Stability options of ±15/±20/±25/±50 ppm are offered with availability depending on temperature range: −20~+70°C, −40~+85°C, −40~+105°C, −40~+125°C.

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FCO-6P-PJ | 2.0×1.6mm | Ultra Low Power Low Jitter FASTXO

SMD 2.0×1.6mm, 0.8ps typ, 25~40mA

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FEATURE

FCO‑6P‑PJ: 2.0×1.6 mm programmable low‑jitter CMOS oscillator—1–200 MHz, 0.8 ps RMS, 1.8/2.5/3.3 V, ±15–50 ppm stability; fast startup for IoT & wearables.

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Datasheet

Product Description

FASTXO Series · Low Power & Low Jitter

FCO‑6P‑PJ — 2.0×1.6 mm Programmable Low‑Power, Low‑Jitter CMOS Oscillator

Name: FCO-6P-PJ
Brand: FCom Fuji Crystal
SKU: FCO-6P-PJ
Rating: 4.9 (17 reviews)

Model: FCO‑6P‑PJ · Package: 2.0×1.6 mm · Output: CMOS · Supply: 1.8/2.5/3.3 V · Range: 1–200 MHz

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FCO‑6P‑PJ 2.0×1.6 mm SMD CMOS oscillator product photo

Ultra‑low RMS phase jitter: 0.8 ps typ (12 kHz–20 MHz @ 50 MHz); 1.5 ps max (Integer), 2.0 ps max (Fractional)
Wide frequency coverage: 1–200 MHz with CMOS output
Supply options: 1.8 V / 2.5 V / 3.3 V
Frequency stability options: ±15 / ±20 / ±25 / ±50 ppm
Tri‑state enable/disable; start‑up ≤8 ms; duty cycle 45–55%
Designed for IoT, smartphones, wearables, game consoles and mobile devices

Overview

FCO‑6P‑PJ is a compact, programmable CMOS oscillator in a 2.0×1.6 mm footprint. It combines wide frequency coverage (1–200 MHz) with exceptionally low phase jitter for timing‑sensitive consumer and IoT designs. Multiple supply options (1.8/2.5/3.3 V), tight ppm stability choices, and tri‑state control make it a versatile drop‑in clock source for dense, battery‑powered systems.

Key Features

RMS phase jitter: 0.8 ps typ (12 kHz–20 MHz @ 50 MHz)
Frequency range: 1–200 MHz
Supply voltage: 1.8 V / 2.5 V / 3.3 V
Duty cycle: 45–55%
Start‑up time: ≤8 ms

Frequency stability options: ±15/±20/±25/±50 ppm
Output load: 15 pF
VDD sensitivity (±5%): ±2 ppm
Aging (1st year @ 25°C): ±3 ppm
Tri‑state thresholds: VIH ≥ 0.7×VDD (Enable), VIL ≤ 0.3×VDD (Disable)

Electrical Specifications

Unless otherwise noted: TA = 25 ± 5°C, RH = 40–70%, CL = 15 pF.

Parameter	Symbol	Min	Typ	Max	Units / Notes
Frequency Range	F	1	—	200	MHz
Supply Voltage	VDD	—	1.8 / 2.5 / 3.3	—	V (typical options)
Output High / Low	VOH / VOL	0.9×VDD	—	0.1×VDD	CMOS levels (min / max)
RMS Phase Jitter (Integer)	PJ	—	0.8	1.5	ps, 12 kHz–20 MHz @ 50 MHz
RMS Phase Jitter (Fractional)	PJ	—	—	2.0	ps, 12 kHz–20 MHz @ 50 MHz
Duty Cycle	TH/T	45		55	%
Start‑up Time	Tosc	—	—	8	ms
Output Load	CL	—	15	—	pF
VDD Sensitivity (±5%)	—	−2	—	+2	ppm
Aging (1st year)	—	—	±3	—	ppm @ 25°C
Tri‑State Input	VIH / VIL	0.7×VDD (EN)	—	0.3×VDD (DIS)	Pin 1 control

Current Consumption (Max, @ 15 pF)
Frequency Band	1.8 V	2.5 V	3.3 V	Units
1 ≤ Fo < 30 MHz	25	27	27	mA
30 ≤ Fo < 75 MHz	25	27	27	mA
75 ≤ Fo < 125 MHz	25	30	30	mA
125 ≤ Fo < 170 MHz	—	35	35	mA
170 ≤ Fo ≤ 200 MHz	—	35	40	mA

Transition Time (10–90%) and Standby
Frequency Band	Tr/Tf (Max)	Standby Current (PD)	Standby Current (OE)
1 ≤ Fo < 10 MHz	≤4 ns	≤400 μA	≤25 mA
10 ≤ Fo < 125 MHz	≤3 ns
125 ≤ Fo ≤ 200 MHz	≤2 ns

Frequency Stability vs Temperature Range

Stability (ppm)	−20~+70°C	−40~+85°C	−40~+105°C	−40~+125°C
±15 ppm	○	×	×	×
±20 ppm	○	△	△	×
±25 ppm	○	○	○	×
±50 ppm	○	○	○	○

○Available△Conditional×Not available

Stability includes calibration at 25°C, operating temperature, input voltage variation, load variation, aging (1st year), shock and vibration.

Recommended Applications

IoT and smart sensors
Smartphones and tablets
Wearable electronics
Game consoles and accessories
General mobile/portable devices

Applications of FCO‑6P‑PJ oscillator in IoT, smartphones, wearables, game consoles and mobile devices

Design Tips

Place a 0.1 μF bypass capacitor as close as possible between VDD and GND pads to ensure optimal performance.
Keep the clock trace short and isolated from high‑slew switching nets to minimize crosstalk and jitter.
Observe logic thresholds for tri‑state control: VIH ≥ 0.7×VDD (Enable), VIL ≤ 0.3×VDD (Disable).
Verify total frequency error budget: ppm stability + VDD sensitivity (±2 ppm for ±5% VDD) + aging.

Resources & Next Steps

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Datasheet

Full electrical specifications, operating conditions and guidelines.

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FAQ

How do OE and PD modes differ?

OE (Output Enable) disables the output while the device remains biased (standby current up to 25 mA). PD (Power‑Down) further reduces current to ≤400 μA. Check your system’s power policy before selecting a mode.

What load can the output drive?

A standard CMOS load of 15 pF is supported. Use short traces and minimize stubs for best signal integrity.

Is 1.8 V operation available at all frequencies?

At the highest frequency bands (≥125 MHz), only 2.5 V and 3.3 V options are available as shown in the current consumption table.

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