Trim by series capacitor or change load caps?

For small corrections, a small series capacitor can raise effective CL; for larger corrections, adjust the load network and layout parasitics. Always re-measure ESR and start-up.

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Q: How much does 1 pF of CL mismatch change frequency?

Depends on cut and band. Around 32.768 kHz (C0≈1.2 pF, C1≈20 fF, CLspec=12.5 pF), −1 pF (lower CL) can raise frequency by roughly +15…+25 ppm. Around 26 MHz (C0≈4 pF, C1≈40 fF, CLspec=10 pF), +1 pF (higher CL) may lower frequency by about −5…−10 ppm. Use the estimator with your crystal’s motional constants.

Q: Does pulling affect phase noise or start-up?

Indirectly. Off-spec CL can change motional current and loop stress, lengthening start-up. Validate across temperature, especially for low-power RTCs.

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Load Capacitance & Frequency Pulling Explained

Release time:

2025-10-08 14:58

Load Capacitance & Frequency Pulling Explained

How the frequency of quartz shifts when the effective load capacitance (CL) deviates from spec. This guide introduces the physics, gives a practical pulling calculator, and shows where designs go wrong—so you can pick the right crystals & oscillators with confidence.

Scope: electronics only (no metaphysical uses). If you are new to timing, start with the Quartz Frequency Pillar and XTAL parameters.

Load capacitance (CL) pulling concept with ppm vs CL curve

How CL Affects Quartz Crystal Oscillator Frequency

In a quartz crystal oscillator, the specified load capacitance determines the nominal frequency. Any deviation between the effective CL on your PCB and the CL specification results in a predictable frequency pulling. Use the estimator below to quantify ppm shift and translate it to time error with our PPM→seconds/day tool.

What is Load Capacitance (CL)?

Manufacturers rate crystals at a specific load capacitance (e.g., 6, 9, 12.5 pF). The oscillator plus PCB parasitics should present this effective load. If the true CL is lower or higher, the oscillation frequency shifts from the nameplate value—this is frequency pulling.

Effective CL quick estimate

For two loading caps to ground, C_L,eff ≈ (C_A·C_B)/(C_A+C_B) + C_stray, where C_stray includes pad/trace and input pin capacitance.

Typical values

Tuning‑fork (32.768 kHz): CL 6–12.5 pF; C0 ≈ 0.8–1.6 pF; C1 ≈ 10–30 fF
AT‑cut (MHz): CL 8–20 pF; C0 ≈ 3–6 pF; C1 ≈ 15–60 fF

Frequency Pulling Estimator

Nominal Frequency f_s (Hz) Specified CL (pF) Effective CL (pF) Shunt Capacitance C0 (pF) Motional Capacitance C1 (fF)

Exact model: Δf ≈ — ppm → Δf ≈ — Hz

Linear approx: Δf ≈ — ppm (small ΔCL)

Exact model uses f_L(CL) = f_s·√(1 + C1/(C0+CL)) and reports the shift from CL_spec to CL_actual. Linear approximation uses Δf/f ≈ −(C1/(2·(C0+CL)²))·ΔCL around CL≈CL_spec.

Estimate CL from Parts

Cap A to GND (pF) Cap B to GND (pF) Pins + Stray (pF)

C_L,eff ≈ — pF (use this as Effective CL)

ppm vs CL (around your spec)

Δppm versus load capacitance around CL_spec: positive shift when CL decreases and negative when CL increases (example: CL_spec=12.5 pF, C0=1.2 pF, C1=20 fF; range 0.5×–1.5×). — Static reference curve of Δppm relative to CL_spec from 0.5× to 1.5×. Use the estimator above for interactive values with your exact motional constants.

Design Boundaries & Good Practices

Stability vs Start‑up

Lower CL reduces motional current (good for power) but lengthens start‑up.
High ESR devices or series resistors can kill loop gain—confirm start‑up across temp.

Tolerance Budget

Include cap tolerance, pin C, and strays in CL error bars (±10–20%).
Use the curve to bound worst‑case Δppm; convert to time with our PPM→seconds/day tool.

Mismatch Case Studies

#1 RTC too fast (CL too low)

Spec: 32,768 Hz, CL=12.5 pF, C0=1.2 pF, C1=20 fF. Actual CL≈9.5 pF (tight layout, smaller caps). Estimator shows positive ppm shift; daily error becomes noticeable. Fix: increase loading caps or add small series cap to raise effective CL.

#2 Radio fails to lock (CL too high)

Spec: 26 MHz XO, CL=10 pF, C0=4 pF, C1=40 fF. Actual CL≈14 pF from long traces. PLL capture range is exceeded at cold—device fails intermittently. Fix: reduce cap values, shorten traces, or move to a TCXO with known CL requirements.

Match a Crystal to Your CL Browse Oscillators (XO/TCXO/OCXO)

FAQ

How much does 1 pF of CL mismatch change frequency?

Rules of thumb depend on the cut and band. Around 32.768 kHz (C0≈1.2 pF, C1≈20 fF, CL_spec=12.5 pF), a −1 pF shift (lower CL) can raise frequency by roughly +15 to +25 ppm. Around 26 MHz (C0≈4 pF, C1≈40 fF, CL_spec=10 pF), a +1 pF shift (higher CL) may lower frequency by about −5 to −10 ppm. Use the estimator above with your crystal’s motional constants for accuracy.

Does pulling affect phase noise or start‑up?

Indirectly. Off‑spec CL can increase loop stress, change motional current, and lengthen start‑up. For low‑power RTCs, running at very low CL reduces current but start‑up becomes slower; validate across temperature.

Should I trim with a series capacitor or change the load caps?

For small corrections, a tiny series capacitor can raise effective CL without swapping both load caps. For large corrections, adjust the load network and layout parasitics; always re‑measure ESR and start‑up.

What tolerances should I budget?

Include MLC capacitor tolerance and temperature drift (often ±5–10%), pin/input capacitance spread, and PCB stray (layout‑dependent). Use the ppm vs CL curve to turn those into worst‑case ppm, then convert to seconds/day.

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