What is the difference between phase noise and jitter?

Phase noise describes the power spectral density of phase fluctuations around a carrier in dBc/Hz (frequency domain). Jitter is the integrated time-domain variation of edge timing in seconds (typically RMS). They describe the same noise, just in different domains.

How do I convert phase noise to RMS jitter?

First, convert L(f) in dBc/Hz to linear single-sideband noise, Sφ(f) ≈ 2·10^(L(f)/10). Integrate over the offset range of interest to get phase variance σφ^2 = ∫ Sφ(f) df. Then convert to time jitter: σt = σφ/(2πf0). Bandwidth choice strongly affects the result.

Which offset bandwidth should I use for jitter integration?

Use the offsets that affect your system’s aperture or loop: e.g., 10 kHz–20 MHz for many SERDES/CMOS clocks, 12 kHz–20 MHz for communications ‘jitter’, or 100 Hz–1 MHz for some RF carriers. Always align with the receive aperture or PLL loop bandwidth.

When should I choose XO, TCXO, or OCXO for low jitter?

For lowest close-in phase noise and long-term stability, OCXOs excel; TCXOs add temperature compensation for better stability with modest power; standard XOs are most power/size efficient but may show higher close-in noise. Select based on jitter target, power, size, and stability needs.

Does better frequency stability (ppm) always mean lower jitter?

Not necessarily. Frequency stability (ppm/ppb) is a slow-time-scale metric, while jitter often comes from integrated phase noise at higher offsets. Devices can be very stable in ppm yet still exhibit higher integrated jitter, and vice versa.

Phase Noise vs Jitter: Why It Matters for Timing-Fuji Crystal (Hong Kong) Electronics Co., Ltd.

Phase Noise vs Jitter: the short answer

Phase noise (frequency domain) quantifies how an oscillator’s energy spreads around its carrier; it is expressed as single-sideband noise L(f) in dBc/Hz at an offset f. Jitter (time domain) is the random variation of zero-crossings or edges, expressed in seconds — commonly RMS.

They are the same underlying phenomenon seen through two lenses. When engineers ask “how many picoseconds RMS jitter?”, they are really asking for the integral of the phase-noise spectrum over a specified offset band, normalized by the carrier frequency.

From L(f) to jitter: the math

The typical conversion uses these steps:

Convert L(f) from dBc/Hz to linear single-sideband PSD: S_φ(f) ≈ 2 · 10^L(f)/10.
Integrate across the offset band of interest to obtain phase variance: σ_φ² = ∫ S_φ(f) df.
Convert phase (radians RMS) to time jitter: σ_t = σ_φ / (2π f₀).

Further reading: Analog Devices MT-008; Texas Instruments SLYT379.

Note: Units matter. Using too wide or too narrow an offset range can under- or over-state jitter by orders of magnitude. Always match the integration to what the receiver or PLL lets through.

Flow diagram: L(f) in dBc/Hz → linear Sφ(f) → integrate over offsets → σφ → divide by 2πf0 → RMS jitter — Formula / process diagram for phase-noise-to-jitter conversion.

Which offset bandwidths matter?

There is no universal bandwidth. Choose the offsets that pass through your loop or aperture: (See Keysight overview.)

Digital clocks / SERDES (reference): 10 kHz–20 MHz (or per standard).
Communications ‘jitter’ metric: 12 kHz–20 MHz (legacy convention).
RF carriers: often 100 Hz–1 MHz for close-in purity (adjust per application).
ADC/DAC sampling clocks: offsets above the loop bandwidth of any preceding PLL.

State your integration band whenever reporting jitter. The same device can be “0.2 ps RMS” or “>1 ps RMS” depending solely on the chosen offsets.

One-shot numeric example (10 kHz–20 MHz)

Goal: Convert datasheet phase noise to integrated RMS jitter in a single pass.

Parameter	Value
Carrier frequency (f₀)	100 MHz
Integration band	10 kHz–20 MHz
Piecewise L(f)	−115 dBc/Hz @ 10 kHz with −20 dB/dec slope to 1 MHz; floor −155 dBc/Hz from 1–20 MHz

Method references ADI MT-008 and Keysight.

Step 1 — Convert to linear SSB phase-noise PSD: Sφ(f) = 2·10^{L(f)/10}.

Step 2 — Integrate piecewise:

10 kHz→1 MHz (−20 dB/dec): Sφ(f) = K·f^{−2}, where K = 2·10^{L(10k)/10}·(10^4)^2 ≈ 6.3246×10^{−4}. Variance σφ₁² = K·(1/f₁ − 1/f₂) ≈ 6.26×10^{−8}.
1 MHz→20 MHz (floor −155 dBc/Hz): Sφ = 2·10^{−155/10} ≈ 6.3246×10^{−16}. Variance σφ₂² = Sφ·Δf ≈ 1.20×10^{−8}.

Step 3 — Combine & convert to time: σφ = √(σφ₁²+σφ₂²) ≈ 2.7318×10^{−4} rad, σt = σφ/(2π f₀) ≈ 4.35×10^{−13} s ≈ 0.435 ps RMS.

Numbers are illustrative but typical for a low-jitter 100 MHz source. Always use the actual datasheet points and your exact band.

Why it matters to real systems

SERDES / PCIe® / Ethernet®: Excess jitter raises bit error rate and fails compliance masks.
RF / GNSS: Close-in noise widens the carrier, degrading sensitivity and lock time.
ADC/DAC: Sampling-clock jitter limits achievable SNR, especially at high input frequencies.
Wireless backhaul & base stations: Phase noise affects EVM and spectral regrowth.

Use case	What matters most	Typical choice
Close-in purity	Low noise <1 kHz offset	OCXO
Temp stability vs power	Low ppm over temperature	TCXO
Small size / low power	Good mid-offset noise	XO

Comparison graphic of XO, TCXO and OCXO phase noise and stability envelopes — Illustrative comparison of XO / TCXO / OCXO trade-offs.

XO vs TCXO vs OCXO: quick selection map

As a rule of thumb for low integrated jitter and close-in phase noise:

OCXO — best close-in phase noise and aging; higher power and warm-up time.
TCXO — excellent temperature stability; good size/power compromise.
XO — simplest and smallest; verify jitter against your bandwidth.

Explore FCom categories: Timing Devices, Crystal Oscillators, TCXOs.

Pro tip: When a PLL or clock cleaner follows the XO/TCXO/OCXO, budget jitter at the PLL output using the loop transfer, not just the reference’s raw phase noise.

Frequently Asked Questions

Why do datasheets list different offset points (e.g., 10 Hz, 100 Hz, 1 kHz)?

Phase noise slopes differ by mechanism (f⁻³, f⁻², f⁻¹, flat). Reporting at several decades helps characterize these regions for integration.

Is RMS jitter the same as period jitter?

RMS cycle-to-cycle or period jitter are related but not identical metrics. Always check the definition; time-interval error (TIE) with a given bandwidth is most comparable to integrated RMS jitter.

How does output format (CMOS vs clipped sine vs LVDS) affect jitter?

Interfaces with faster slew and lower noise coupling (e.g., LVDS) generally yield lower edge-uncertainty at the receiver threshold than high-swing CMOS in a noisy environment.

Can a low-ppm device still have high jitter?

Yes. PPM stability and jitter are largely orthogonal. Temperature and aging shape slow frequency drift; jitter comes from integrated short-term phase noise.

Process graphic: specify f0 and offset band, integrate phase noise, convert to RMS jitter, verify against budget — Process checklist to turn datasheet phase noise into a system jitter number.

External references :

Fuji Crystal

Phase Noise vs Jitter: Why It Matters for Timing

Phase Noise vs Jitter — Why It Matters for Timing